drm/i915: Clear flushing lists on GPU reset (9375e446) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_drv.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -385,6 +385,12 @@ int i965_reset(struct drm_device *dev, u8 flags)
		*/
		i915_gem_retire_requests(dev);

		/* Remove anything from the flushing lists. The GPU cache is likely
		* to be lost on reset along with the data, so simply move the
		* lost bo to the inactive list.
		*/
		i915_gem_reset_flushing_list(dev);

		/*
		* Set the domains we want to reset (GRDOM/bits 2 and 3) as
		* well as the reset bit (GR/bit 0). Setting the GR bit

+1 −0

Original line number	Diff line number	Diff line
		@@ -997,6 +997,7 @@ int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
		int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
		bool interruptible);
		void i915_gem_retire_requests(struct drm_device *dev);
		void i915_gem_reset_flushing_list(struct drm_device *dev);
		void i915_gem_clflush_object(struct drm_gem_object *obj);
		int i915_gem_object_set_domain(struct drm_gem_object *obj,
		uint32_t read_domains,

+16 −0

Original line number	Diff line number	Diff line
		@@ -1683,6 +1683,22 @@ i915_get_gem_seqno(struct drm_device *dev,
		return ring->get_gem_seqno(dev, ring);
		}

		void i915_gem_reset_flushing_list(struct drm_device *dev)
		{
		struct drm_i915_private *dev_priv = dev->dev_private;

		while (!list_empty(&dev_priv->mm.flushing_list)) {
		struct drm_i915_gem_object *obj_priv;

		obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
		struct drm_i915_gem_object,
		list);

		obj_priv->base.write_domain = 0;
		i915_gem_object_move_to_inactive(&obj_priv->base);
		}
		}

		/**
		* This function clears the request list as sequence numbers are passed.
		*/