Commit 93737fe9 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-5.2' of... 

Merge tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

Our usual bunch of changes, this time, it's mainly:

 - Export a new clock for the MBUS controller on the A13
 - H6 fixes to support a finer clocking of the video and VPU engines
 - Add some Kconfig options
 - Some bit offset fixes

* tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun5i: Export the MBUS clock
  clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
  clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
  clk: sunxi-ng: h6: Preset hdmi-cec clock parent
  clk: sunxi: Add Kconfig options
  clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
  clk: sunxi-ng: Allow DE clock to set parent rate
parents 9e98c678 c77cebac

drivers/clk/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -310,6 +310,7 @@ source "drivers/clk/qcom/Kconfig" 
source "drivers/clk/renesas/Kconfig"

source "drivers/clk/samsung/Kconfig"

source "drivers/clk/sprd/Kconfig"

source "drivers/clk/sunxi/Kconfig"

source "drivers/clk/sunxi-ng/Kconfig"

source "drivers/clk/tegra/Kconfig"

source "drivers/clk/ti/Kconfig"

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+2 −1
Original line number Diff line number Diff line
@@ -531,7 +531,8 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 


static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };

static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,

				 0x104, 0, 4, 24, 3, BIT(31), 0);

				 0x104, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);



static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };

static const u8 tcon0_table[] = { 0, 2, };

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+15 −4
Original line number Diff line number Diff line
@@ -266,7 +266,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, 
				       0, 4,	/* M */

				       24, 1,	/* mux */

				       BIT(31),	/* gate */

				       0);

				       CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",

		      0x60c, BIT(0), 0);
@@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 
				       0, 3,	/* M */

				       24, 1,	/* mux */

				       BIT(31),	/* gate */

				       0);

				       CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",

		      0x69c, BIT(0), 0);
@@ -656,6 +656,8 @@ static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; 
static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {

	{ .index = 1, .div = 36621 },

};



#define SUN50I_H6_HDMI_CEC_CLK_REG		0xb10

static struct ccu_mux hdmi_cec_clk = {

	.enable		= BIT(31),
@@ -689,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", 
			       tcon_lcd0_parents, 0xb60,

			       24, 3,	/* mux */

			       BIT(31),	/* gate */

			       0);

			       CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",

		      0xb7c, BIT(0), 0);
@@ -704,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", 
				  8, 2,		/* P */

				  24, 3,	/* mux */

				  BIT(31),	/* gate */

				  0);

				  CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",

		      0xb9c, BIT(0), 0);
@@ -1200,6 +1202,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) 
	val &= ~(GENMASK(21, 16) | BIT(0));

	writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);



	/*

	 * First clock parent (osc32K) is unusable for CEC. But since there

	 * is no good way to force parent switch (both run with same frequency),

	 * just set second clock parent here.

	 */

	val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG);

	val |= BIT(24);

	writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);



	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc);

}

drivers/clk/sunxi-ng/ccu-sun5i.h

+0 −4
Original line number Diff line number Diff line
@@ -60,10 +60,6 @@ 


/* The rest of the module clocks are exported */



#define CLK_MBUS		99



/* And finally the IEP clock */



#define CLK_NUMBER		(CLK_IEP + 1)



#endif /* _CCU_SUN5I_H_ */

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

+3 −2
Original line number Diff line number Diff line
@@ -513,8 +513,9 @@ static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0); 


static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);



static const char * const csi_mclk_parents[] = { "pll-de", "osc24M" };

static const u8 csi_mclk_table[] = { 3, 5 };

static const char * const csi_mclk_parents[] = { "pll-video0", "pll-de",

						 "osc24M" };

static const u8 csi_mclk_table[] = { 0, 3, 5 };

static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",

				       csi_mclk_parents, csi_mclk_table,

				       0x134,

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