x86/apic: Initialize interrupt mode after timer init (935356ce) · Commits · 戴 / test

A cold or warm boot through BIOS sets the APIC in default interrupt delivery mode. A dump-capture kernel will not go through a BIOS reset and leave the interrupt delivery mode in the state which was active on the crashed kernel, but the dump kernel startup code assumes default delivery mode which can result in interrupt delivery/handling to fail. To solve this problem, it's required to set up the final interrupt delivery mode as soon as possible. As IOAPIC setup needs the timer initialized for verifying the timer interrupt delivery mode, the earliest point is right after timer setup in late_time_init(). That results in the following init order: 1) Set up the legacy timer, if applicable on the platform 2) Set up APIC/IOAPIC which includes the verification of the legacy timer interrupt delivery. 3) TSC calibration 4) Local APIC timer setup Signed-off-by:

Dou Liyang <douly.fnst@cn.fujitsu.com> Signed-off-by:

Thomas Gleixner <tglx@linutronix.de> Cc: yinghai@kernel.org Cc: bhe@redhat.com Link: https://lkml.kernel.org/r/1505293975-26005-12-git-send-email-douly.fnst@cn.fujitsu.com

arch/x86/kernel/apic/apic.c

+0 −2

Original line number	Diff line number	Diff line
		@@ -2423,8 +2423,6 @@ void __init apic_bsp_setup(bool upmode)
		#ifdef CONFIG_UP_LATE_INIT
		void __init up_late_init(void)
		{
		x86_init.irqs.intr_mode_init();

		if (apic_intr_mode == APIC_PIC)
		return;

arch/x86/kernel/smpboot.c

+3 −4

Original line number	Diff line number	Diff line
		@@ -1263,8 +1263,9 @@ static void __init smp_get_logical_apicid(void)
		}

		/*
		* Prepare for SMP bootup. The MP table or ACPI has been read
		* earlier. Just do some sanity checking here and enable APIC mode.
		* Prepare for SMP bootup.
		* @max_cpus: configured maximum number of CPUs, It is a legacy parameter
		* for common interface support.
		*/
		void __init native_smp_prepare_cpus(unsigned int max_cpus)
		{
		@@ -1296,8 +1297,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)

		set_cpu_sibling_map(0);

		x86_init.irqs.intr_mode_init();

		smp_sanity_check();

		switch (apic_intr_mode) {

arch/x86/kernel/time.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -84,6 +84,11 @@ void __init hpet_time_init(void)
		static __init void x86_late_time_init(void)
		{
		x86_init.timers.timer_init();
		/*
		* After PIT/HPET timers init, select and setup
		* the final interrupt mode for delivering IRQs.
		*/
		x86_init.irqs.intr_mode_init();
		tsc_init();
		}

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