Merge tag 'renesas-dt-for-v4.9' of... (93329cd0) · Commits · 戴 / test

arch/arm/boot/dts/r8a7792-blanche.dts

+48 −0

Original line number	Diff line number	Diff line
		@@ -50,6 +50,9 @@
		reg-io-width = <4>;
		vddvario-supply = <&d3_3v>;
		vdd33a-supply = <&d3_3v>;

		pinctrl-0 = <&lan89218_pins>;
		pinctrl-names = "default";
		};
		};

		@@ -57,10 +60,55 @@
		clock-frequency = <20000000>;
		};

		&can_clk {
		clock-frequency = <48000000>;
		};

		&pfc {
		scif0_pins: scif0 {
		groups = "scif0_data";
		function = "scif0";
		};

		scif3_pins: scif3 {
		groups = "scif3_data";
		function = "scif3";
		};

		lan89218_pins: lan89218 {
		intc {
		groups = "intc_irq0";
		function = "intc";
		};
		lbsc {
		groups = "lbsc_ex_cs0";
		function = "lbsc";
		};
		};

		can0_pins: can0 {
		groups = "can0_data", "can_clk";
		function = "can0";
		};
		};

		&scif0 {
		pinctrl-0 = <&scif0_pins>;
		pinctrl-names = "default";

		status = "okay";
		};

		&scif3 {
		pinctrl-0 = <&scif3_pins>;
		pinctrl-names = "default";

		status = "okay";
		};

		&can0 {
		pinctrl-0 = <&can0_pins>;
		pinctrl-names = "default";

		status = "okay";
		};

arch/arm/boot/dts/r8a7792.dtsi

+498 −2

Original line number	Diff line number	Diff line
		@@ -18,6 +18,21 @@
		#address-cells = <2>;
		#size-cells = <2>;

		aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		vin0 = &vin0;
		vin1 = &vin1;
		vin2 = &vin2;
		vin3 = &vin3;
		vin4 = &vin4;
		vin5 = &vin5;
		};

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		@@ -108,6 +123,179 @@
		#power-domain-cells = <1>;
		};

		pfc: pin-controller@e6060000 {
		compatible = "renesas,pfc-r8a7792";
		reg = <0 0xe6060000 0 0x144>;
		};

		gpio0: gpio@e6050000 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6050000 0 0x50>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 29>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio1: gpio@e6051000 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6051000 0 0x50>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 23>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio2: gpio@e6052000 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6052000 0 0x50>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio3: gpio@e6053000 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6053000 0 0x50>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 28>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio4: gpio@e6054000 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6054000 0 0x50>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 17>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio5: gpio@e6055000 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6055000 0 0x50>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 17>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio6: gpio@e6055100 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6055100 0 0x50>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 17>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio7: gpio@e6055200 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6055200 0 0x50>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 224 17>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio8: gpio@e6055300 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6055300 0 0x50>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 256 17>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio9: gpio@e6055400 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6055400 0 0x50>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 288 17>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio10: gpio@e6055500 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6055500 0 0x50>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 320 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		gpio11: gpio@e6055600 {
		compatible = "renesas,gpio-r8a7792",
		"renesas,gpio-rcar";
		reg = <0 0xe6055600 0 0x50>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 352 30>;
		#interrupt-cells = <2>;
		interrupt-controller;
		clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		dmac0: dma-controller@e6700000 {
		compatible = "renesas,dmac-r8a7792",
		"renesas,rcar-dmac";
		@@ -262,6 +450,18 @@
		status = "disabled";
		};

		sdhi0: sd@ee100000 {
		compatible = "renesas,sdhi-r8a7792";
		reg = <0 0xee100000 0 0x328>;
		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
		<&dmac1 0xcd>, <&dmac1 0xce>;
		dma-names = "tx", "rx", "tx", "rx";
		clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		jpu: jpeg-codec@fe980000 {
		compatible = "renesas,jpu-r8a7792",
		"renesas,rcar-gen2-jpu";
		@@ -271,6 +471,203 @@
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		};

		avb: ethernet@e6800000 {
		compatible = "renesas,etheravb-r8a7792",
		"renesas,etheravb-rcar-gen2";
		reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		/* I2C doesn't need pinmux */
		i2c0: i2c@e6508000 {
		compatible = "renesas,i2c-r8a7792";
		reg = <0 0xe6508000 0 0x40>;
		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <6>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		i2c1: i2c@e6518000 {
		compatible = "renesas,i2c-r8a7792";
		reg = <0 0xe6518000 0 0x40>;
		interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <6>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		i2c2: i2c@e6530000 {
		compatible = "renesas,i2c-r8a7792";
		reg = <0 0xe6530000 0 0x40>;
		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <6>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		i2c3: i2c@e6540000 {
		compatible = "renesas,i2c-r8a7792";
		reg = <0 0xe6540000 0 0x40>;
		interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <6>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		i2c4: i2c@e6520000 {
		compatible = "renesas,i2c-r8a7792";
		reg = <0 0xe6520000 0 0x40>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <6>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		i2c5: i2c@e6528000 {
		compatible = "renesas,i2c-r8a7792";
		reg = <0 0xe6528000 0 0x40>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <110>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		du: display@feb00000 {
		compatible = "renesas,du-r8a7792";
		reg = <0 0xfeb00000 0 0x40000>;
		reg-names = "du";
		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7792_CLK_DU0>,
		<&mstp7_clks R8A7792_CLK_DU1>;
		clock-names = "du.0", "du.1";
		status = "disabled";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		du_out_rgb0: endpoint {
		};
		};
		port@1 {
		reg = <1>;
		du_out_rgb1: endpoint {
		};
		};
		};
		};

		can0: can@e6e80000 {
		compatible = "renesas,can-r8a7792",
		"renesas,rcar-gen2-can";
		reg = <0 0xe6e80000 0 0x1000>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
		<&rcan_clk>, <&can_clk>;
		clock-names = "clkp1", "clkp2", "can_clk";
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		can1: can@e6e88000 {
		compatible = "renesas,can-r8a7792",
		"renesas,rcar-gen2-can";
		reg = <0 0xe6e88000 0 0x1000>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
		<&rcan_clk>, <&can_clk>;
		clock-names = "clkp1", "clkp2", "can_clk";
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		vin0: video@e6ef0000 {
		compatible = "renesas,vin-r8a7792",
		"renesas,rcar-gen2-vin";
		reg = <0 0xe6ef0000 0 0x1000>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		vin1: video@e6ef1000 {
		compatible = "renesas,vin-r8a7792",
		"renesas,rcar-gen2-vin";
		reg = <0 0xe6ef1000 0 0x1000>;
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		vin2: video@e6ef2000 {
		compatible = "renesas,vin-r8a7792",
		"renesas,rcar-gen2-vin";
		reg = <0 0xe6ef2000 0 0x1000>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		vin3: video@e6ef3000 {
		compatible = "renesas,vin-r8a7792",
		"renesas,rcar-gen2-vin";
		reg = <0 0xe6ef3000 0 0x1000>;
		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		vin4: video@e6ef4000 {
		compatible = "renesas,vin-r8a7792",
		"renesas,rcar-gen2-vin";
		reg = <0 0xe6ef4000 0 0x1000>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		vin5: video@e6ef5000 {
		compatible = "renesas,vin-r8a7792",
		"renesas,rcar-gen2-vin";
		reg = <0 0xe6ef5000 0 0x1000>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
		status = "disabled";
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
		compatible = "renesas,r8a7792-cpg-clocks",
		@@ -291,6 +688,13 @@
		clock-div = <2>;
		clock-mult = <1>;
		};
		zx_clk: zx {
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
		#clock-cells = <0>;
		clock-div = <3>;
		clock-mult = <1>;
		};
		zs_clk: zs {
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
		@@ -298,6 +702,13 @@
		clock-div = <6>;
		clock-mult = <1>;
		};
		hp_clk: hp {
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
		#clock-cells = <0>;
		clock-div = <12>;
		clock-mult = <1>;
		};
		p_clk: p {
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
		@@ -319,6 +730,27 @@
		clock-div = <8>;
		clock-mult = <1>;
		};
		sd_clk: sd {
		compatible = "fixed-factor-clock";
		clocks = <&pll1_div2_clk>;
		#clock-cells = <0>;
		clock-div = <8>;
		clock-mult = <1>;
		};
		rcan_clk: rcan {
		compatible = "fixed-factor-clock";
		clocks = <&pll1_div2_clk>;
		#clock-cells = <0>;
		clock-div = <49>;
		clock-mult = <1>;
		};
		zg_clk: zg {
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
		#clock-cells = <0>;
		clock-div = <5>;
		clock-mult = <1>;
		};

		/* Gate clocks */
		mstp1_clks: mstp1_clks@e6150134 {
		@@ -341,6 +773,15 @@
		>;
		clock-output-names = "sys-dmac1", "sys-dmac0";
		};
		mstp3_clks: mstp3_clks@e615013c {
		compatible = "renesas,r8a7792-mstp-clocks",
		"renesas,cpg-mstp-clocks";
		reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
		clocks = <&sd_clk>;
		#clock-cells = <1>;
		renesas,clock-indices = <R8A7792_CLK_SDHI0>;
		clock-output-names = "sdhi0";
		};
		mstp4_clks: mstp4_clks@e6150140 {
		compatible = "renesas,r8a7792-mstp-clocks",
		"renesas,cpg-mstp-clocks";
		@@ -355,15 +796,62 @@
		"renesas,cpg-mstp-clocks";
		reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
		clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
		<&p_clk>, <&p_clk>;
		<&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
		#clock-cells = <1>;
		clock-indices = <
		R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
		R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
		R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
		R8A7792_CLK_DU1 R8A7792_CLK_DU0
		>;
		clock-output-names = "hscif1", "hscif0", "scif3",
		"scif2", "scif1", "scif0";
		"scif2", "scif1", "scif0",
		"du1", "du0";
		};
		mstp8_clks: mstp8_clks@e6150990 {
		compatible = "renesas,r8a7792-mstp-clocks",
		"renesas,cpg-mstp-clocks";
		reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
		clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
		<&zg_clk>, <&zg_clk>, <&hp_clk>;
		#clock-cells = <1>;
		clock-indices = <
		R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
		R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
		R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
		R8A7792_CLK_ETHERAVB
		>;
		clock-output-names = "vin5", "vin4", "vin3", "vin2",
		"vin1", "vin0", "etheravb";
		};
		mstp9_clks: mstp9_clks@e6150994 {
		compatible = "renesas,r8a7792-mstp-clocks",
		"renesas,cpg-mstp-clocks";
		reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
		clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
		<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
		<&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
		<&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
		<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
		#clock-cells = <1>;
		clock-indices = <
		R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
		R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
		R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
		R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
		R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
		R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
		R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
		R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
		R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
		R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
		>;
		clock-output-names =
		"gpio7", "gpio6", "gpio5", "gpio4",
		"gpio3", "gpio2", "gpio1", "gpio0",
		"gpio11", "gpio10", "can1", "can0",
		"gpio9", "gpio8", "i2c5", "i2c4",
		"i2c3", "i2c2", "i2c1", "i2c0";
		};
		};

		@@ -382,4 +870,12 @@
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
		};

		/* External CAN clock */
		can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
		};
		};

arch/arm/boot/dts/r8a7794-silk.dts

+70 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,17 @@
		* kind, whether express or implied.
		*/

		/*
		* SSI-AK4643
		*
		* SW1: 2-1: AK4643
		* 2-3: ADV7511
		*
		* This command is required before playback/capture:
		*
		* amixer set "LINEOUT Mixer DACL" on
		*/

		/dts-v1/;
		#include "r8a7794.dtsi"
		#include <dt-bindings/gpio/gpio.h>
		@@ -119,6 +130,29 @@
		#clock-cells = <0>;
		clock-frequency = <74250000>;
		};

		x9_clk: audio_clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12288000>;
		};

		sound {
		compatible = "simple-audio-card";

		simple-audio-card,format = "left_j";
		simple-audio-card,bitclock-master = <&soundcodec>;
		simple-audio-card,frame-master = <&soundcodec>;

		simple-audio-card,cpu {
		sound-dai = <&rcar_sound>;
		};

		soundcodec: simple-audio-card,codec {
		sound-dai = <&ak4643>;
		clocks = <&x9_clk>;
		};
		};
		};

		&extal_clk {
		@@ -193,6 +227,16 @@
		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
		function = "du1";
		};

		ssi_pins: sound {
		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
		function = "ssi";
		};

		audio_clk_pins: audio_clk {
		groups = "audio_clkc";
		function = "audio_clk";
		};
		};

		&scif2 {
		@@ -230,6 +274,12 @@
		status = "okay";
		clock-frequency = <400000>;

		ak4643: codec@12 {
		compatible = "asahi-kasei,ak4643";
		#sound-dai-cells = <0>;
		reg = <0x12>;
		};

		composite-in@20 {
		compatible = "adi,adv7180";
		reg = <0x20>;
		@@ -392,3 +442,23 @@
		};
		};
		};

		&rcar_sound {
		pinctrl-0 = <&ssi_pins &audio_clk_pins>;
		pinctrl-names = "default";
		status = "okay";

		/* Single DAI */
		#sound-dai-cells = <0>;

		rcar_sound,dai {
		dai0 {
		playback = <&ssi0>;
		capture = <&ssi1>;
		};
		};
		};

		&ssi1 {
		shared-pin;
		};

arch/arm/boot/dts/r8a7794.dtsi

+292 −1

File changed.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/r8a7794-clock.h

+25 −0

Original line number	Diff line number	Diff line
		@@ -67,6 +67,7 @@
		#define R8A7794_CLK_IRQC 7

		/* MSTP5 */
		#define R8A7794_CLK_AUDIO_DMAC0 2
		#define R8A7794_CLK_PWM 23

		/* MSTP7 */
		@@ -107,6 +108,30 @@
		#define R8A7794_CLK_I2C1 30
		#define R8A7794_CLK_I2C0 31

		/* MSTP10 */
		#define R8A7794_CLK_SSI_ALL 5
		#define R8A7794_CLK_SSI9 6
		#define R8A7794_CLK_SSI8 7
		#define R8A7794_CLK_SSI7 8
		#define R8A7794_CLK_SSI6 9
		#define R8A7794_CLK_SSI5 10
		#define R8A7794_CLK_SSI4 11
		#define R8A7794_CLK_SSI3 12
		#define R8A7794_CLK_SSI2 13
		#define R8A7794_CLK_SSI1 14
		#define R8A7794_CLK_SSI0 15
		#define R8A7794_CLK_SCU_ALL 17
		#define R8A7794_CLK_SCU_DVC1 18
		#define R8A7794_CLK_SCU_DVC0 19
		#define R8A7794_CLK_SCU_CTU1_MIX1 20
		#define R8A7794_CLK_SCU_CTU0_MIX0 21
		#define R8A7794_CLK_SCU_SRC6 25
		#define R8A7794_CLK_SCU_SRC5 26
		#define R8A7794_CLK_SCU_SRC4 27
		#define R8A7794_CLK_SCU_SRC3 28
		#define R8A7794_CLK_SCU_SRC2 29
		#define R8A7794_CLK_SCU_SRC1 30

		/* MSTP11 */
		#define R8A7794_CLK_SCIFA3 6
		#define R8A7794_CLK_SCIFA4 7

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