Commit 9325c9f0 authored by Jesse Barnes's avatar Jesse Barnes Committed by Keith Packard
Browse files

drm/i915: set bpc for DP transcoder 



This may not be the default value, so pull the bpc out of the pipe reg
and write it to the DP transcoder so proper dithering and signaling
occurs.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent e9bcff5c

drivers/gpu/drm/i915/intel_display.c

+2 −1
Original line number Diff line number Diff line
@@ -2622,6 +2622,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 
	/* For PCH DP, enable TRANS_DP_CTL */

	if (HAS_PCH_CPT(dev) &&

	    intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {

		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;

		reg = TRANS_DP_CTL(pipe);

		temp = I915_READ(reg);

		temp &= ~(TRANS_DP_PORT_SEL_MASK |
@@ -2629,7 +2630,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 
			  TRANS_DP_BPC_MASK);

		temp |= (TRANS_DP_OUTPUT_ENABLE |

			 TRANS_DP_ENH_FRAMING);

		temp |= TRANS_DP_8BPC;

		temp |= bpc << 9; /* same format but at 11:9 */



		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)

			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;

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