Commit 931f5492 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915: Make pipe/transcoder offsets not depend on enum values 



Depending on the transcoder enum values to translate from transcoder
to pipe/transcoder register addresses can easily break if we add a new
transcoder. So remove the dependency by using named initializers.

Suggested-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181120092325.21249-1-imre.deak@intel.com
parent 3c64ea8c

drivers/gpu/drm/i915/i915_pci.c

+38 −14
Original line number Diff line number Diff line
@@ -33,16 +33,30 @@ 
#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)



#define GEN_DEFAULT_PIPEOFFSETS \

	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \

			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }

	.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET,	\

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = PIPE_C_OFFSET, \

		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \

	}, \

	.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \

		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \

	}



#define GEN_CHV_PIPEOFFSETS \

	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \

			  CHV_PIPE_C_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   CHV_TRANSCODER_C_OFFSET }

	.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET, \

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \

	}, \

	.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \

	}



#define CURSOR_OFFSETS \

	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
@@ -592,12 +606,22 @@ static const struct intel_device_info intel_cannonlake_info = { 


#define GEN11_FEATURES \

	GEN10_FEATURES, \

	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \

			  PIPE_C_OFFSET, PIPE_EDP_OFFSET, \

			  PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \

			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \

	.pipe_offsets = { \

		[TRANSCODER_A] = PIPE_A_OFFSET, \

		[TRANSCODER_B] = PIPE_B_OFFSET, \

		[TRANSCODER_C] = PIPE_C_OFFSET, \

		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \

		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \

		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \

	}, \

	.trans_offsets = { \

		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \

		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \

		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \

		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \

		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \

		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \

	}, \

	GEN(11), \

	.ddb_size = 2048, \

	.has_logical_ring_elsq = 1

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