Commit 930a93a5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Radeon and intel fixes mostly, one fix to the mgag200 driver to not
  hang on certain server variants."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (32 commits)
  drm/radeon: fix typo in function header comment
  drm/radeon/kms: implement timestamp userspace query (v2)
  drm/radeon/kms: add MSAA texture support for r600-evergreen
  drm/radeon/kms: reorder code in r600_check_texture_resource
  drm/radeon: fence virtual address and free it once idle v4
  drm/radeon: fix some missing parens in asic macros
  drm/radeon: add some new SI pci ids
  drm/radeon: fix ordering in pll picking on dce4+
  drm/radeon: do not reenable crtc after moving vram start address
  drm/radeon: fix bank tiling parameters on cayman
  drm/radeon: fix bank tiling parameters on evergreen
  drm/radeon: fix bank tiling parameters on SI
  drm/radeon: properly handle crtc powergating
  drm/radeon: properly handle SS overrides on TN (v2)
  drm/radeon/dce4+: set a more reasonable cursor watermark
  drm/radeon: fix handling for ddc type 5 on combios
  drm/mgag200: fix G200ER pll picking algorithm
  drm/edid: Fix potential memory leak in edid_load()
  drm/udl: Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(.. [1]
  drm/radeon/kms: allow "invalid" DB formats as a means to disable DB
  ...
parents f43e04ec 7bac6b46

drivers/char/agp/intel-agp.h

+34 −5
Original line number Diff line number Diff line
@@ -242,13 +242,42 @@ 
#define PCI_DEVICE_ID_INTEL_HASWELL_HB			0x0400 /* Desktop */

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG	0x0422

#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB		0x0404 /* Mobile */

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG	0x0426

#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB		0x0408 /* Server */

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV		0x0c16 /* SDV */

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG	0x042a

#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB		0x0c04

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG	0x0C02

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG	0x0C12

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG	0x0C22

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG	0x0C06

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG	0x0C16

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG	0x0C26

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG	0x0C0A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG	0x0C1A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG	0x0C2A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG	0x0A02

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG	0x0A12

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG	0x0A22

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG	0x0A06

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG	0x0A16

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG	0x0A26

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG	0x0A0A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG	0x0A1A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG	0x0A2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG	0x0D12

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG	0x0D22

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG	0x0D32

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG	0x0D16

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG	0x0D26

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG	0x0D36

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG	0x0D1A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG	0x0D2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG	0x0D3A



#endif

drivers/char/agp/intel-gtt.c

+59 −1
Original line number Diff line number Diff line
@@ -1502,15 +1502,73 @@ static const struct intel_gtt_driver_description { 
	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,

	    "Haswell", &sandybridge_gtt_driver },

	{ 0, NULL, NULL }

};

drivers/gpu/drm/drm_edid_load.c

+5 −3
Original line number Diff line number Diff line
@@ -119,7 +119,7 @@ static int edid_load(struct drm_connector *connector, char *name, 
{

	const struct firmware *fw;

	struct platform_device *pdev;

	u8 *fwdata = NULL, *edid;

	u8 *fwdata = NULL, *edid, *new_edid;

	int fwsize, expected;

	int builtin = 0, err = 0;

	int i, valid_extensions = 0;
@@ -195,12 +195,14 @@ static int edid_load(struct drm_connector *connector, char *name, 
		    "\"%s\" for connector \"%s\"\n", valid_extensions,

		    edid[0x7e], name, connector_name);

		edid[0x7e] = valid_extensions;

		edid = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH,

		new_edid = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH,

		    GFP_KERNEL);

		if (edid == NULL) {

		if (new_edid == NULL) {

			err = -ENOMEM;

			kfree(edid);

			goto relfw_out;

		}

		edid = new_edid;

	}



	connector->display_info.raw_edid = edid;

drivers/gpu/drm/i915/i915_drv.c

+30 −1
Original line number Diff line number Diff line
@@ -346,11 +346,40 @@ static const struct pci_device_id pciidlist[] = { /* aka */ 
	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */

	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */

	INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */

	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */

	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */

	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */

	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */

	INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */

	INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */

	INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */

	INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */

	INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */

	INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */

	INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */

	INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */

	INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */

	INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */

	INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */

	INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */

	INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */

	INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */

	INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */

	INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */

	INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */

	INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */

	INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */

	INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */

	INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */

	INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */

	INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */

	INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */

	INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */

	INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */

	INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */

	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */

	INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */

	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),

	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),

drivers/gpu/drm/i915/i915_gem_context.c

+0 −1
Original line number Diff line number Diff line
@@ -451,7 +451,6 @@ int i915_switch_context(struct intel_ring_buffer *ring, 
	struct drm_i915_file_private *file_priv = NULL;

	struct i915_hw_context *to;

	struct drm_i915_gem_object *from_obj = ring->last_context_obj;

	int ret;



	if (dev_priv->hw_contexts_disabled)

		return 0;

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