clk: qoriq: add LS1021A core pll mux options (92df3a9b) · Commits · 戴 / test

This allows to clock the cores with 1 GHz, 500 MHz and 250 MHz. Signed-off-by:

drivers/clk/clk-qoriq.c

+9 −1

Original line number	Diff line number	Diff line
		@@ -244,6 +244,14 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
		},
		};

		static const struct clockgen_muxinfo ls1021a_cmux = {
		{
		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
		}
		};

		static const struct clockgen_muxinfo ls1028a_hwa1 = {
		{
		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
		@@ -577,7 +585,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
		{
		.compat = "fsl,ls1021a-clockgen",
		.cmux_groups = {
		&t1023_cmux
		&ls1021a_cmux
		},
		.cmux_to_group = {
		0, -1