Commit 92bbdaeb authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn:Update SPG mode VCN global tiling 



Update Static Power Gate mode VCN global tiling

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 298dc39a

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+18 −0
Original line number Diff line number Diff line
@@ -325,6 +325,24 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 
			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

	WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,

			adev->gfx.config.gb_addr_config);

}



static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)

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