Commit 92b19ff5 authored by Dan Williams's avatar Dan Williams
Browse files

cleanup IORESOURCE_CACHEABLE vs ioremap() 



Quoting Arnd:
    I was thinking the opposite approach and basically removing all uses
    of IORESOURCE_CACHEABLE from the kernel. There are only a handful of
    them.and we can probably replace them all with hardcoded
    ioremap_cached() calls in the cases they are actually useful.

All existing usages of IORESOURCE_CACHEABLE call ioremap() instead of
ioremap_nocache() if the resource is cacheable, however ioremap() is
uncached by default. Clearly none of the existing usages care about the
cacheability. Particularly devm_ioremap_resource() never worked as
advertised since it always fell back to plain ioremap().

Clean this up as the new direction we want is to convert
ioremap_<type>() usages to memremap(..., flags).

Suggested-by: default avatarArnd Bergmann <arnd@arndb.de>
Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 2584cf83

arch/arm/mach-clps711x/board-cdb89712.c

+1 −1
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ static struct physmap_flash_data cdb89712_bootrom_pdata __initdata = { 


static struct resource cdb89712_bootrom_resources[] __initdata = {

	DEFINE_RES_NAMED(CS7_PHYS_BASE, SZ_128, "BOOTROM", IORESOURCE_MEM |

			 IORESOURCE_CACHEABLE | IORESOURCE_READONLY),

			 IORESOURCE_READONLY),

};



static struct platform_device cdb89712_bootrom_pdev __initdata = {

arch/powerpc/kernel/pci_of_scan.c

+1 −1
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev) 
			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];

		} else if (i == dev->rom_base_reg) {

			res = &dev->resource[PCI_ROM_RESOURCE];

			flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;

			flags |= IORESOURCE_READONLY;

		} else {

			printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);

			continue;

arch/sparc/kernel/pci.c

+1 −2
Original line number Diff line number Diff line
@@ -231,8 +231,7 @@ static void pci_parse_of_addrs(struct platform_device *op, 
			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];

		} else if (i == dev->rom_base_reg) {

			res = &dev->resource[PCI_ROM_RESOURCE];

			flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE

			      | IORESOURCE_SIZEALIGN;

			flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;

		} else {

			printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);

			continue;

drivers/pci/probe.c

+1 −2
Original line number Diff line number Diff line
@@ -326,8 +326,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 
		struct resource *res = &dev->resource[PCI_ROM_RESOURCE];

		dev->rom_base_reg = rom;

		res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |

				IORESOURCE_READONLY | IORESOURCE_CACHEABLE |

				IORESOURCE_SIZEALIGN;

				IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;

		__pci_read_base(dev, pci_bar_mem32, res, rom);

	}

}

drivers/pnp/manager.c

+0 −2
Original line number Diff line number Diff line
@@ -97,8 +97,6 @@ static int pnp_assign_mem(struct pnp_dev *dev, struct pnp_mem *rule, int idx) 
	/* ??? rule->flags restricted to 8 bits, all tests bogus ??? */

	if (!(rule->flags & IORESOURCE_MEM_WRITEABLE))

		res->flags |= IORESOURCE_READONLY;

	if (rule->flags & IORESOURCE_MEM_CACHEABLE)

		res->flags |= IORESOURCE_CACHEABLE;

	if (rule->flags & IORESOURCE_MEM_RANGELENGTH)

		res->flags |= IORESOURCE_RANGELENGTH;

	if (rule->flags & IORESOURCE_MEM_SHADOWABLE)

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