KVM: VMX: Set IGMT bit in EPT entry (928d4bf7) · Commits · 戴 / test

There is a potential issue that, when guest using pagetable without vmexit when EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory, which would be inconsistent with host side and would cause host MCE due to inconsistent cache attribute. The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default memory type to protect host (notice that all memory mapped by KVM should be WB). Signed-off-by:

Sheng Yang <sheng@linux.intel.com> Signed-off-by:

Avi Kivity <avi@redhat.com>

arch/x86/kvm/vmx.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -3564,7 +3564,8 @@ static int __init vmx_init(void)
		bypass_guest_pf = 0;
		kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK \|
		VMX_EPT_WRITABLE_MASK \|
		VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
		VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT \|
		VMX_EPT_IGMT_BIT);
		kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
		VMX_EPT_EXECUTABLE_MASK);
		kvm_enable_tdp();

arch/x86/kvm/vmx.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -352,6 +352,7 @@ enum vmcs_field {
		#define VMX_EPT_READABLE_MASK 0x1ull
		#define VMX_EPT_WRITABLE_MASK 0x2ull
		#define VMX_EPT_EXECUTABLE_MASK 0x4ull
		#define VMX_EPT_IGMT_BIT (1ull << 6)

		#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul

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