Commit 925f566c authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add set and get clock for testing purposes 



add dc_set_clock
add dc_get_clock

this is for testing and diagnostics to get/set DPPCLK and DISPCLK.

Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 30db43b6

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

+22 −1
Original line number Diff line number Diff line
@@ -316,11 +316,32 @@ void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) 
	}

}



void dcn2_get_clock(struct clk_mgr *clk_mgr,

		struct dc_state *context,

			enum dc_clock_type clock_type,

			struct dc_clock_config *clock_cfg)

{



	if (clock_type == DC_CLOCK_TYPE_DISPCLK) {

		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;

		clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;

		clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;

		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;

	}

	if (clock_type == DC_CLOCK_TYPE_DPPCLK) {

		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;

		clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;

		clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;

		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;

	}

}



static struct clk_mgr_funcs dcn2_funcs = {

	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,

	.update_clocks = dcn2_update_clocks,

	.init_clocks = dcn2_init_clocks,

	.enable_pme_wa = dcn2_enable_pme_wa

	.enable_pme_wa = dcn2_enable_pme_wa,

	.get_clock = dcn2_get_clock,

};

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

+5 −0
Original line number Diff line number Diff line
@@ -45,4 +45,9 @@ void dcn20_clk_mgr_construct(struct dc_context *ctx, 


uint32_t dentist_get_did_from_divider(int divider);



void dcn2_get_clock(struct clk_mgr *clk_mgr,

		struct dc_state *context,

			enum dc_clock_type clock_type,

			struct dc_clock_config *clock_cfg);



#endif //__DCN20_CLK_MGR_H__

drivers/gpu/drm/amd/display/dc/core/dc.c

+11 −0
Original line number Diff line number Diff line
@@ -2431,3 +2431,14 @@ void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx 
	info->fClock					= (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;

	info->phyClock					= (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;

}

enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)

{

	if (dc->hwss.set_clock)

		return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);

	return DC_ERROR_UNEXPECTED;

}

void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)

{

	if (dc->hwss.get_clock)

		dc->hwss.get_clock(dc, clock_type, clock_cfg);

}

drivers/gpu/drm/amd/display/dc/dc.h

+5 −0
Original line number Diff line number Diff line
@@ -252,7 +252,10 @@ enum wm_report_mode { 
struct dc_clocks {

	int dispclk_khz;

	int max_supported_dppclk_khz;

	int max_supported_dispclk_khz;

	int dppclk_khz;

	int bw_dppclk_khz; /*a copy of dppclk_khz*/

	int bw_dispclk_khz;

	int dcfclk_khz;

	int socclk_khz;

	int dcfclk_deep_sleep_khz;
@@ -1041,6 +1044,8 @@ unsigned int dc_get_target_backlight_pwm(struct dc *dc); 


bool dc_is_dmcu_initialized(struct dc *dc);



enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);

void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);

#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)

/*******************************************************************************

 * DSC Interfaces

drivers/gpu/drm/amd/display/dc/dc_types.h

+13 −0
Original line number Diff line number Diff line
@@ -726,6 +726,19 @@ struct AsicStateEx { 
	unsigned int phyClock;

};





enum dc_clock_type {

	DC_CLOCK_TYPE_DISPCLK = 0,

	DC_CLOCK_TYPE_DPPCLK        = 1,

};



struct dc_clock_config {

	uint32_t max_clock_khz;

	uint32_t min_clock_khz;

	uint32_t bw_requirequired_clock_khz;

	uint32_t current_clock_khz;/*current clock in use*/

};



#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

/* DSC DPCD capabilities */

union dsc_slice_caps1 {

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