Commit 924bb1f9 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/dwc' 

- Fix designware-ep Header Type check (Hou Zhiqiang)

- Use DBI accessors instead of own config accessors (Rob Herring)

- Allow overriding bridge pci_ops (Rob Herring)

- Allow root and child buses to have different pci_ops (Rob Herring)

- Add default dwc pci_ops.map_bus (Rob Herring)

- Use pci_ops for root config space accessors in al, exynos, histb,
  keystone, kirin, meson, tegra (Rob Herring)

- Remove dwc own/other config accessor ops (Rob Herring)

- Use generic config accessors in dwc (Rob Herring)

- Also call .add_bus() callback for root bus (Rob Herring)

- Convert keystone .scan_bus() callback to use pci_ops.add_bus (Rob
  Herring)

- Convert dwc to use pci_host_probe() (Rob Herring)

- Remove dwc root_bus pointer (Rob Herring)

- Remove storing of PCI resources in dwc-specific structs (Rob Herring)

- Simplify config space handling (Rob Herring)

- Drop keystone duplicated DT num-viewport handling (Rob Herring)

- Check CONFIG_PCI_MSI in dw_pcie_msi_init() instead of duplicating it in
  all the drivers (Rob Herring)

- Remove imx6 duplicate PCIE_LINK_WIDTH_SPEED_CONTROL definition (Rob
  Herring)

- Add dwc num_lanes for use when it's lacking from DT (Rob Herring)

- Ensure "Fast Link Mode" simulation environment setting is cleared (Rob
  Herring)

- Drop meson duplicate number of lanes setup (Rob Herring)

- Drop meson unnecessary RC config space init (Rob Herring)

- Rework meson config and dwc port logic register accesses (Rob Herring)

- Use common PCI register definitions in imx6 and qcom (Rob Herring)

- Search for DesignWare PCIe Capability instead of hard-coding its location
  (Rob Herring)

- Use common DesignWare register definitions in tegra (Rob Herring)

- Drop keystone unused DBI2 code (Rob Herring)

- Make dwc ATU accessors private (Rob Herring)

- Centralize link gen setting in dwc (Rob Herring)

- Set PORT_LINK_DLL_LINK_EN in common dwc setup code (Rob Herring)

- Drop intel-gw unnecessary DT 'device_type' checking (Rob Herring)

- Move intel-gw PCI_CAP_ID_EXP discovery to the single place it's used (Rob
  Herring)

- Drop intel-gw unused max_width (Rob Herring)

- Move N_FTS (fast training sequence) setup to common dwc setup (Rob
  Herring)

- Convert spear13xx, tegra194 to use DBI accessors (Rob Herring)

- Add multiple PFs support for DWC (Xiaowei Bao)

- Add MSI-X doorbell mode for endpoint mode (Xiaowei Bao)

- Update MSI/MSI-X capability management for endpoints (Xiaowei Bao)

- Add layerscape ls1088a and ls2088a compatible strings (Xiaowei Bao)

- Update layerscape MSI/MSI-X management (Xiaowei Bao)

- Use doorbell to support MSI-X on layerscape (Xiaowei Bao)

- Add layerscape endpoint mode support for ls1088a and ls2088a (Xiaowei
  Bao)

- Add layerscape ls1088a node to DT (Xiaowei Bao)

- Add Freescale/Layerscape ls1088a to endpoint test (Xiaowei Bao)

- Add endpoint test driver data for Layerscape PCIe controllers (Hou
  Zhiqiang)

- Fix 'cast truncates bits from constant value' warning (Gustavo Pimentel)

- Add uniphier iATU register description (Kunihiko Hayashi)

- Add common iATU register support (Kunihiko Hayashi)

- Remove keystone iATU register mapping in favor of generic dwc support
  (Kunihiko Hayashi)

- Skip PCIE_MSI_INTR0* programming if MSI is disabled (Jisheng Zhang)

- Fix MSI page leakage in suspend/resume (Jisheng Zhang)

- Check whether link is up before attempting config access (best-effort fix
  even though it's racy) (Hou Zhiqiang)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()
  PCI: dwc: Fix MSI page leakage in suspend/resume
  PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled
  PCI: keystone: Remove iATU register mapping
  PCI: dwc: Add common iATU register support
  dt-bindings: PCI: uniphier-ep: Add iATU register description
  dt-bindings: PCI: uniphier: Add iATU register description
  PCI: dwc: Fix 'cast truncates bits from constant value'
  misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers
  misc: pci_endpoint_test: Add LS1088a in pci_device_id table
  PCI: layerscape: Add EP mode support for ls1088a and ls2088a
  PCI: layerscape: Modify the MSIX to the doorbell mode
  PCI: layerscape: Modify the way of getting capability with different PEX
  PCI: layerscape: Fix some format issue of the code
  dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a
  PCI: designware-ep: Modify MSI and MSIX CAP way of finding
  PCI: designware-ep: Move the function of getting MSI capability forward
  PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
  PCI: designware-ep: Add multiple PFs support for DWC
  PCI: dwc: Use DBI accessors
  PCI: dwc: Move N_FTS setup to common setup
  PCI: dwc/intel-gw: Drop unused max_width
  PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
  PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property
  PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
  PCI: dwc: Centralize link gen setting
  PCI: dwc: Make ATU accessors private
  PCI: dwc: Remove read_dbi2 code
  PCI: dwc/tegra: Use common Designware port logic register definitions
  PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
  PCI: dwc/qcom: Use common PCI register definitions
  PCI: dwc/imx6: Use common PCI register definitions
  PCI: dwc/meson: Rework PCI config and DW port logic register accesses
  PCI: dwc/meson: Drop unnecessary RC config space initialization
  PCI: dwc/meson: Drop the duplicate number of lanes setup
  PCI: dwc: Ensure FAST_LINK_MODE is cleared
  PCI: dwc: Add a 'num_lanes' field to struct dw_pcie
  PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL
  PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
  PCI: dwc/keystone: Drop duplicated 'num-viewport'
  PCI: dwc: Simplify config space handling
  PCI: dwc: Remove storing of PCI resources
  PCI: dwc: Remove root_bus pointer
  PCI: dwc: Convert to use pci_host_probe()
  PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus
  PCI: Also call .add_bus() callback for root bus
  PCI: dwc: Use generic config accessors
  PCI: dwc: Remove dwc specific config accessor ops
  PCI: dwc: histb: Use pci_ops for root config space accessors
  PCI: dwc: exynos: Use pci_ops for root config space accessors
  PCI: dwc: kirin: Use pci_ops for root config space accessors
  PCI: dwc: meson: Use pci_ops for root config space accessors
  PCI: dwc: tegra: Use pci_ops for root config space accessors
  PCI: dwc: keystone: Use pci_ops for config space accessors
  PCI: dwc: al: Use pci_ops for child config space accessors
  PCI: dwc: Add a default pci_ops.map_bus for root port
  PCI: dwc: Allow overriding bridge pci_ops
  PCI: dwc: Use DBI accessors instead of own config accessors
  PCI: Allow root and child buses to have different pci_ops
  PCI: designware-ep: Fix the Header Type check
parents a78f2e07 15b23906

Documentation/devicetree/bindings/pci/layerscape-pci.txt

+2 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ Required properties: 
        "fsl,ls1028a-pcie"

  EP mode:

	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"

	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"

	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"

- reg: base addresses and lengths of the PCIe controller register blocks.

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml

+14 −6
Original line number Diff line number Diff line
@@ -23,14 +23,22 @@ properties: 
    const: socionext,uniphier-pro5-pcie-ep



  reg:

    maxItems: 4

    minItems: 4

    maxItems: 5



  reg-names:

    items:

    oneOf:

      - items:

        - const: dbi

        - const: dbi2

        - const: link

        - const: addr_space

      - items:

        - const: dbi

        - const: dbi2

        - const: link

        - const: addr_space

        - const: atu



  clocks:

    maxItems: 2

Documentation/devicetree/bindings/pci/uniphier-pcie.txt

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ Required properties: 
    "dbi"    - controller configuration registers

    "link"   - SoC-specific glue layer registers

    "config" - PCIe configuration space

    "atu"    - iATU registers for DWC version 4.80 or later

- clocks: A phandle to the clock gate for PCIe glue layer including

	the host controller.

- resets: A phandle to the reset line for PCIe glue layer including

drivers/misc/pci_endpoint_test.c

+7 −1
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 


#define PCI_DEVICE_ID_TI_J721E			0xb00d

#define PCI_DEVICE_ID_TI_AM654			0xb00c

#define PCI_DEVICE_ID_LS1088A			0x80c0



#define is_am654_pci_dev(pdev)		\

		((pdev)->device == PCI_DEVICE_ID_TI_AM654)
@@ -945,7 +946,12 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { 
	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),

	  .driver_data = (kernel_ulong_t)&default_data,

	},

	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },

	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),

	  .driver_data = (kernel_ulong_t)&default_data,

	},

	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),

	  .driver_data = (kernel_ulong_t)&default_data,

	},

	{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },

	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),

	  .driver_data = (kernel_ulong_t)&am654_data

drivers/pci/controller/dwc/pci-dra7xx.c

+17 −29
Original line number Diff line number Diff line
@@ -73,8 +73,6 @@ 
#define	LINK_UP						BIT(16)

#define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF



#define EXP_CAP_ID_OFFSET				0x70



#define	PCIECTRL_TI_CONF_INTX_ASSERT			0x0124

#define	PCIECTRL_TI_CONF_INTX_DEASSERT			0x0128
@@ -91,7 +89,6 @@ struct dra7xx_pcie { 
	void __iomem		*base;		/* DT ti_conf */

	int			phy_count;	/* DT phy-names count */

	struct phy		**phy;

	int			link_gen;

	struct irq_domain	*irq_domain;

	enum dw_pcie_device_mode mode;

};
@@ -142,33 +139,12 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci) 
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);

	struct device *dev = pci->dev;

	u32 reg;

	u32 exp_cap_off = EXP_CAP_ID_OFFSET;



	if (dw_pcie_link_up(pci)) {

		dev_err(dev, "link is already up\n");

		return 0;

	}



	if (dra7xx->link_gen == 1) {

		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,

			     4, &reg);

		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);

			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_write(pci->dbi_base + exp_cap_off +

				      PCI_EXP_LNKCAP, 4, reg);

		}



		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,

			     2, &reg);

		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);

			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_write(pci->dbi_base + exp_cap_off +

				      PCI_EXP_LNKCTL2, 2, reg);

		}

	}



	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);

	reg |= LTSSM_EN;

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
@@ -490,7 +466,9 @@ static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = { 
static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct device *dev = pci->dev;

	u32 ctrl, num_ctrls;

	int ret;



	pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip;
@@ -506,7 +484,21 @@ static int dra7xx_pcie_msi_host_init(struct pcie_port *pp) 
				    ~0);

	}



	return dw_pcie_allocate_domains(pp);

	ret = dw_pcie_allocate_domains(pp);

	if (ret)

		return ret;



	pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,

					   sizeof(pp->msi_msg),

					   DMA_FROM_DEVICE,

					   DMA_ATTR_SKIP_CPU_SYNC);

	ret = dma_mapping_error(dev, pp->msi_data);

	if (ret) {

		dev_err(dev, "Failed to map MSI data\n");

		pp->msi_data = 0;

		dw_pcie_free_msi(pp);

	}

	return ret;

}



static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
@@ -937,10 +929,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) 
	reg &= ~LTSSM_EN;

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);



	dra7xx->link_gen = of_pci_get_max_link_speed(np);

	if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)

		dra7xx->link_gen = 2;



	switch (mode) {

	case DW_PCIE_RC_TYPE:

		if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {

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