Commit 923b8f50 authored Jul 02, 2014 by Steve Capper Committed by Catalin Marinas Jul 04, 2014

arm64: mm: Make icache synchronisation logic huge page aware



The __sync_icache_dcache routine will only flush the dcache for the
first page of a compound page, potentially leading to stale icache
data residing further on in a hugetlb page.

This patch addresses this issue by taking into consideration the
order of the page when flushing the dcache.

Reported-by: Mark Brown <broonie@linaro.org>
Tested-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: <stable@vger.kernel.org> # v3.11+

parent f3b766a2

arch/arm64/mm/flush.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
		return;

		if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
		__flush_dcache_area(page_address(page), PAGE_SIZE);
		__flush_dcache_area(page_address(page),
		PAGE_SIZE << compound_order(page));
		__flush_icache_all();
		} else if (icache_is_aivivt()) {
		__flush_icache_all();

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