Commit 9228d8b2 authored by Jacob Keller's avatar Jacob Keller Committed by Tony Nguyen
Browse files

ice: join format strings to same line as ice_debug 



When printing messages with ice_debug, align the printed string to the
origin line of the message in order to ease debugging and tracking
messages back to their source.

Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 34d8461a

drivers/net/ethernet/intel/ice/ice_common.c

+34 −68
Original line number Diff line number Diff line
@@ -904,8 +904,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw) 
	/* Query the allocated resources for Tx scheduler */

	status = ice_sched_query_res_alloc(hw);

	if (status) {

		ice_debug(hw, ICE_DBG_SCHED,

			  "Failed to get scheduler allocated resources\n");

		ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");

		goto err_unroll_alloc;

	}
@@ -1045,8 +1044,7 @@ enum ice_status ice_check_reset(struct ice_hw *hw) 
	}



	if (cnt == grst_timeout) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Global reset polling failed to complete.\n");

		ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");

		return ICE_ERR_RESET_FAILED;

	}
@@ -1064,16 +1062,14 @@ enum ice_status ice_check_reset(struct ice_hw *hw) 
	for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {

		reg = rd32(hw, GLNVM_ULD) & uld_mask;

		if (reg == uld_mask) {

			ice_debug(hw, ICE_DBG_INIT,

				  "Global reset processes done. %d\n", cnt);

			ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);

			break;

		}

		mdelay(10);

	}



	if (cnt == ICE_PF_RESET_WAIT_COUNT) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",

		ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",

			  reg);

		return ICE_ERR_RESET_FAILED;

	}
@@ -1125,8 +1121,7 @@ static enum ice_status ice_pf_reset(struct ice_hw *hw) 
	}



	if (cnt == ICE_PF_RESET_WAIT_COUNT) {

		ice_debug(hw, ICE_DBG_INIT,

			  "PF reset polling failed to complete.\n");

		ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");

		return ICE_ERR_RESET_FAILED;

	}
@@ -1579,8 +1574,7 @@ ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 
		goto ice_acquire_res_exit;



	if (status)

		ice_debug(hw, ICE_DBG_RES,

			  "resource %d acquire type %d failed.\n", res, access);

		ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);



	/* If necessary, poll until the current lock owner timeouts */

	timeout = time_left;
@@ -1603,11 +1597,9 @@ ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 
ice_acquire_res_exit:

	if (status == ICE_ERR_AQ_NO_WORK) {

		if (access == ICE_RES_WRITE)

			ice_debug(hw, ICE_DBG_RES,

				  "resource indicates no work to do.\n");

			ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");

		else

			ice_debug(hw, ICE_DBG_RES,

				  "Warning: ICE_ERR_AQ_NO_WORK not expected\n");

			ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n");

	}

	return status;

}
@@ -1793,66 +1785,53 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 
	switch (cap) {

	case ICE_AQC_CAPS_VALID_FUNCTIONS:

		caps->valid_functions = number;

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: valid_functions (bitmap) = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,

			  caps->valid_functions);

		break;

	case ICE_AQC_CAPS_SRIOV:

		caps->sr_iov_1_1 = (number == 1);

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: sr_iov_1_1 = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix,

			  caps->sr_iov_1_1);

		break;

	case ICE_AQC_CAPS_DCB:

		caps->dcb = (number == 1);

		caps->active_tc_bitmap = logical_id;

		caps->maxtc = phys_id;

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: dcb = %d\n", prefix, caps->dcb);

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: active_tc_bitmap = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);

		ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,

			  caps->active_tc_bitmap);

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: maxtc = %d\n", prefix, caps->maxtc);

		ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);

		break;

	case ICE_AQC_CAPS_RSS:

		caps->rss_table_size = number;

		caps->rss_table_entry_width = logical_id;

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: rss_table_size = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,

			  caps->rss_table_size);

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: rss_table_entry_width = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,

			  caps->rss_table_entry_width);

		break;

	case ICE_AQC_CAPS_RXQS:

		caps->num_rxq = number;

		caps->rxq_first_id = phys_id;

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: num_rxq = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,

			  caps->num_rxq);

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: rxq_first_id = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,

			  caps->rxq_first_id);

		break;

	case ICE_AQC_CAPS_TXQS:

		caps->num_txq = number;

		caps->txq_first_id = phys_id;

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: num_txq = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,

			  caps->num_txq);

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: txq_first_id = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,

			  caps->txq_first_id);

		break;

	case ICE_AQC_CAPS_MSIX:

		caps->num_msix_vectors = number;

		caps->msix_vector_first_id = phys_id;

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: num_msix_vectors = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,

			  caps->num_msix_vectors);

		ice_debug(hw, ICE_DBG_INIT,

			  "%s: msix_vector_first_id = %d\n", prefix,

		ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,

			  caps->msix_vector_first_id);

		break;

	case ICE_AQC_CAPS_PENDING_NVM_VER:
@@ -1905,8 +1884,7 @@ ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 
	if (hw->dev_caps.num_funcs > 4) {

		/* Max 4 TCs per port */

		caps->maxtc = 4;

		ice_debug(hw, ICE_DBG_INIT,

			  "reducing maxtc to %d (based on #ports)\n",

		ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",

			  caps->maxtc);

	}

}
@@ -1974,11 +1952,9 @@ ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 
		GLQF_FD_SIZE_FD_BSIZE_S;

	func_p->fd_fltr_best_effort = val;



	ice_debug(hw, ICE_DBG_INIT,

		  "func caps: fd_fltr_guar = %d\n",

	ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",

		  func_p->fd_fltr_guar);

	ice_debug(hw, ICE_DBG_INIT,

		  "func caps: fd_fltr_best_effort = %d\n",

	ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",

		  func_p->fd_fltr_best_effort);

}
@@ -2027,8 +2003,7 @@ ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
		default:

			/* Don't list common capabilities as unknown */

			if (!found)

				ice_debug(hw, ICE_DBG_INIT,

					  "func caps: unknown capability[%d]: 0x%x\n",

				ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",

					  i, cap);

			break;

		}
@@ -2161,8 +2136,7 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 
		default:

			/* Don't list common capabilities as unknown */

			if (!found)

				ice_debug(hw, ICE_DBG_INIT,

					  "dev caps: unknown capability[%d]: 0x%x\n",

				ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",

					  i, cap);

			break;

		}
@@ -2619,8 +2593,7 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 


	/* Ensure that only valid bits of cfg->caps can be turned on. */

	if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {

		ice_debug(hw, ICE_DBG_PHY,

			  "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",

		ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",

			  cfg->caps);



		cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
@@ -3068,8 +3041,7 @@ enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 
		status = ice_update_link_info(pi);



		if (status)

			ice_debug(pi->hw, ICE_DBG_LINK,

				  "get link status error, status = %d\n",

			ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",

				  status);

	}
@@ -3794,8 +3766,7 @@ ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 
		 * of the endianness of the machine.

		 */

		if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {

			ice_debug(hw, ICE_DBG_QCTX,

				  "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",

			ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",

				  f, ce_info[f].width, ce_info[f].size_of);

			continue;

		}
@@ -4293,8 +4264,7 @@ ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 
	status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,

					ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);

	if (status) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Failed to read link override TLV.\n");

		ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");

		return status;

	}
@@ -4305,8 +4275,7 @@ ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 
	/* link options first */

	status = ice_read_sr_word(hw, tlv_start, &buf);

	if (status) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Failed to read override link options.\n");

		ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");

		return status;

	}

	ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
@@ -4317,8 +4286,7 @@ ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 
	offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;

	status = ice_read_sr_word(hw, offset, &buf);

	if (status) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Failed to read override phy config.\n");

		ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");

		return status;

	}

	ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
@@ -4328,8 +4296,7 @@ ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 
	for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {

		status = ice_read_sr_word(hw, (offset + i), &buf);

		if (status) {

			ice_debug(hw, ICE_DBG_INIT,

				  "Failed to read override link options.\n");

			ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");

			return status;

		}

		/* shift 16 bits at a time to fill 64 bits */
@@ -4342,8 +4309,7 @@ ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 
	for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {

		status = ice_read_sr_word(hw, (offset + i), &buf);

		if (status) {

			ice_debug(hw, ICE_DBG_INIT,

				  "Failed to read override link options.\n");

			ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");

			return status;

		}

		/* shift 16 bits at a time to fill 64 bits */

drivers/net/ethernet/intel/ice/ice_controlq.c

+14 −28
Original line number Diff line number Diff line
@@ -717,8 +717,7 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw) 
		if (status != ICE_ERR_AQ_FW_CRITICAL)

			break;



		ice_debug(hw, ICE_DBG_AQ_MSG,

			  "Retry Admin Queue init due to FW critical error\n");

		ice_debug(hw, ICE_DBG_AQ_MSG, "Retry Admin Queue init due to FW critical error\n");

		ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);

		msleep(ICE_CTL_Q_ADMIN_INIT_MSEC);

	} while (retry++ < ICE_CTL_Q_ADMIN_INIT_TIMEOUT);
@@ -813,8 +812,7 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq) 
	details = ICE_CTL_Q_DETAILS(*sq, ntc);



	while (rd32(hw, cq->sq.head) != ntc) {

		ice_debug(hw, ICE_DBG_AQ_MSG,

			  "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));

		ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));

		memset(desc, 0, sizeof(*desc));

		memset(details, 0, sizeof(*details));

		ntc++;
@@ -852,8 +850,7 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len) 


	len = le16_to_cpu(cq_desc->datalen);



	ice_debug(hw, ICE_DBG_AQ_DESC,

		  "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",

	ice_debug(hw, ICE_DBG_AQ_DESC, "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",

		  le16_to_cpu(cq_desc->opcode),

		  le16_to_cpu(cq_desc->flags),

		  le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval));
@@ -925,8 +922,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
	cq->sq_last_status = ICE_AQ_RC_OK;



	if (!cq->sq.count) {

		ice_debug(hw, ICE_DBG_AQ_MSG,

			  "Control Send queue not initialized.\n");

		ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send queue not initialized.\n");

		status = ICE_ERR_AQ_EMPTY;

		goto sq_send_command_error;

	}
@@ -938,8 +934,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 


	if (buf) {

		if (buf_size > cq->sq_buf_size) {

			ice_debug(hw, ICE_DBG_AQ_MSG,

				  "Invalid buffer size for Control Send queue: %d.\n",

			ice_debug(hw, ICE_DBG_AQ_MSG, "Invalid buffer size for Control Send queue: %d.\n",

				  buf_size);

			status = ICE_ERR_INVAL_SIZE;

			goto sq_send_command_error;
@@ -952,8 +947,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 


	val = rd32(hw, cq->sq.head);

	if (val >= cq->num_sq_entries) {

		ice_debug(hw, ICE_DBG_AQ_MSG,

			  "head overrun at %d in the Control Send Queue ring\n",

		ice_debug(hw, ICE_DBG_AQ_MSG, "head overrun at %d in the Control Send Queue ring\n",

			  val);

		status = ICE_ERR_AQ_EMPTY;

		goto sq_send_command_error;
@@ -971,8 +965,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
	 * called in a separate thread in case of asynchronous completions.

	 */

	if (ice_clean_sq(hw, cq) == 0) {

		ice_debug(hw, ICE_DBG_AQ_MSG,

			  "Error: Control Send Queue is full.\n");

		ice_debug(hw, ICE_DBG_AQ_MSG, "Error: Control Send Queue is full.\n");

		status = ICE_ERR_AQ_FULL;

		goto sq_send_command_error;

	}
@@ -1000,8 +993,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
	}



	/* Debug desc and buffer */

	ice_debug(hw, ICE_DBG_AQ_DESC,

		  "ATQ: Control Send queue desc and buffer:\n");

	ice_debug(hw, ICE_DBG_AQ_DESC, "ATQ: Control Send queue desc and buffer:\n");



	ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
@@ -1026,8 +1018,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
			u16 copy_size = le16_to_cpu(desc->datalen);



			if (copy_size > buf_size) {

				ice_debug(hw, ICE_DBG_AQ_MSG,

					  "Return len %d > than buf len %d\n",

				ice_debug(hw, ICE_DBG_AQ_MSG, "Return len %d > than buf len %d\n",

					  copy_size, buf_size);

				status = ICE_ERR_AQ_ERROR;

			} else {
@@ -1036,8 +1027,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
		}

		retval = le16_to_cpu(desc->retval);

		if (retval) {

			ice_debug(hw, ICE_DBG_AQ_MSG,

				  "Control Send Queue command 0x%04X completed with error 0x%X\n",

			ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send Queue command 0x%04X completed with error 0x%X\n",

				  le16_to_cpu(desc->opcode),

				  retval);
@@ -1050,8 +1040,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
		cq->sq_last_status = (enum ice_aq_err)retval;

	}



	ice_debug(hw, ICE_DBG_AQ_MSG,

		  "ATQ: desc and buffer writeback:\n");

	ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n");



	ice_debug_cq(hw, (void *)desc, buf, buf_size);
@@ -1067,8 +1056,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
			ice_debug(hw, ICE_DBG_AQ_MSG, "Critical FW error.\n");

			status = ICE_ERR_AQ_FW_CRITICAL;

		} else {

			ice_debug(hw, ICE_DBG_AQ_MSG,

				  "Control Send Queue Writeback timeout.\n");

			ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send Queue Writeback timeout.\n");

			status = ICE_ERR_AQ_TIMEOUT;

		}

	}
@@ -1124,8 +1112,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
	mutex_lock(&cq->rq_lock);



	if (!cq->rq.count) {

		ice_debug(hw, ICE_DBG_AQ_MSG,

			  "Control Receive queue not initialized.\n");

		ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive queue not initialized.\n");

		ret_code = ICE_ERR_AQ_EMPTY;

		goto clean_rq_elem_err;

	}
@@ -1147,8 +1134,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 
	flags = le16_to_cpu(desc->flags);

	if (flags & ICE_AQ_FLAG_ERR) {

		ret_code = ICE_ERR_AQ_ERROR;

		ice_debug(hw, ICE_DBG_AQ_MSG,

			  "Control Receive Queue Event 0x%04X received with error 0x%X\n",

		ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n",

			  le16_to_cpu(desc->opcode),

			  cq->rq_last_status);

	}

drivers/net/ethernet/intel/ice/ice_flex_pipe.c

+8 −16
Original line number Diff line number Diff line
@@ -709,8 +709,7 @@ ice_acquire_global_cfg_lock(struct ice_hw *hw, 
	if (!status)

		mutex_lock(&ice_global_cfg_lock_sw);

	else if (status == ICE_ERR_AQ_NO_WORK)

		ice_debug(hw, ICE_DBG_PKG,

			  "Global config lock: No work to do\n");

		ice_debug(hw, ICE_DBG_PKG, "Global config lock: No work to do\n");



	return status;

}
@@ -909,8 +908,7 @@ ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count) 
					   last, &offset, &info, NULL);



		if (status) {

			ice_debug(hw, ICE_DBG_PKG,

				  "Update pkg failed: err %d off %d inf %d\n",

			ice_debug(hw, ICE_DBG_PKG, "Update pkg failed: err %d off %d inf %d\n",

				  status, offset, info);

			break;

		}
@@ -988,8 +986,7 @@ ice_dwnld_cfg_bufs(struct ice_hw *hw, struct ice_buf *bufs, u32 count) 
		/* Save AQ status from download package */

		hw->pkg_dwnld_status = hw->adminq.sq_last_status;

		if (status) {

			ice_debug(hw, ICE_DBG_PKG,

				  "Pkg download failed: err %d off %d inf %d\n",

			ice_debug(hw, ICE_DBG_PKG, "Pkg download failed: err %d off %d inf %d\n",

				  status, offset, info);



			break;
@@ -1083,8 +1080,7 @@ ice_init_pkg_info(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr) 
			  meta_seg->pkg_ver.update, meta_seg->pkg_ver.draft,

			  meta_seg->pkg_name);

	} else {

		ice_debug(hw, ICE_DBG_INIT,

			  "Did not find metadata segment in driver package\n");

		ice_debug(hw, ICE_DBG_INIT, "Did not find metadata segment in driver package\n");

		return ICE_ERR_CFG;

	}
@@ -1101,8 +1097,7 @@ ice_init_pkg_info(struct ice_hw *hw, struct ice_pkg_hdr *pkg_hdr) 
			  seg_hdr->seg_format_ver.draft,

			  seg_hdr->seg_id);

	} else {

		ice_debug(hw, ICE_DBG_INIT,

			  "Did not find ice segment in driver package\n");

		ice_debug(hw, ICE_DBG_INIT, "Did not find ice segment in driver package\n");

		return ICE_ERR_CFG;

	}
@@ -1318,8 +1313,7 @@ ice_chk_pkg_compat(struct ice_hw *hw, struct ice_pkg_hdr *ospkg, 
		    (*seg)->hdr.seg_format_ver.minor >

			pkg->pkg_info[i].ver.minor) {

			status = ICE_ERR_FW_DDP_MISMATCH;

			ice_debug(hw, ICE_DBG_INIT,

				  "OS package is not compatible with NVM.\n");

			ice_debug(hw, ICE_DBG_INIT, "OS package is not compatible with NVM.\n");

		}

		/* done processing NVM package so break */

		break;
@@ -1387,8 +1381,7 @@ enum ice_status ice_init_pkg(struct ice_hw *hw, u8 *buf, u32 len) 
	ice_init_pkg_hints(hw, seg);

	status = ice_download_pkg(hw, seg);

	if (status == ICE_ERR_AQ_NO_WORK) {

		ice_debug(hw, ICE_DBG_INIT,

			  "package previously loaded - no work.\n");

		ice_debug(hw, ICE_DBG_INIT, "package previously loaded - no work.\n");

		status = 0;

	}
@@ -3261,8 +3254,7 @@ ice_has_prof_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl) 
		if (ent->profile_cookie == hdl)

			return true;



	ice_debug(hw, ICE_DBG_INIT,

		  "Characteristic list for VSI group %d not found.\n",

	ice_debug(hw, ICE_DBG_INIT, "Characteristic list for VSI group %d not found.\n",

		  vsig);

	return false;

}

drivers/net/ethernet/intel/ice/ice_flow.c

+3 −6
Original line number Diff line number Diff line
@@ -745,8 +745,7 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk, 


	status = ice_flow_proc_segs(hw, params);

	if (status) {

		ice_debug(hw, ICE_DBG_FLOW,

			  "Error processing a flow's packet segments\n");

		ice_debug(hw, ICE_DBG_FLOW, "Error processing a flow's packet segments\n");

		goto out;

	}
@@ -835,8 +834,7 @@ ice_flow_assoc_prof(struct ice_hw *hw, enum ice_block blk, 
		if (!status)

			set_bit(vsi_handle, prof->vsis);

		else

			ice_debug(hw, ICE_DBG_FLOW,

				  "HW profile add failed, %d\n",

			ice_debug(hw, ICE_DBG_FLOW, "HW profile add failed, %d\n",

				  status);

	}
@@ -867,8 +865,7 @@ ice_flow_disassoc_prof(struct ice_hw *hw, enum ice_block blk, 
		if (!status)

			clear_bit(vsi_handle, prof->vsis);

		else

			ice_debug(hw, ICE_DBG_FLOW,

				  "HW profile remove failed, %d\n",

			ice_debug(hw, ICE_DBG_FLOW, "HW profile remove failed, %d\n",

				  status);

	}

drivers/net/ethernet/intel/ice/ice_nvm.c

+9 −18
Original line number Diff line number Diff line
@@ -73,8 +73,7 @@ ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data, 


	/* Verify the length of the read if this is for the Shadow RAM */

	if (read_shadow_ram && ((offset + inlen) > (hw->nvm.sr_words * 2u))) {

		ice_debug(hw, ICE_DBG_NVM,

			  "NVM error: requested offset is beyond Shadow RAM limit\n");

		ice_debug(hw, ICE_DBG_NVM, "NVM error: requested offset is beyond Shadow RAM limit\n");

		return ICE_ERR_PARAM;

	}
@@ -397,8 +396,7 @@ static enum ice_status ice_get_orom_ver_info(struct ice_hw *hw) 
	status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,

					ICE_SR_BOOT_CFG_PTR);

	if (status) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Failed to read Boot Configuration Block TLV.\n");

		ice_debug(hw, ICE_DBG_INIT, "Failed to read Boot Configuration Block TLV.\n");

		return status;

	}
@@ -406,8 +404,7 @@ static enum ice_status ice_get_orom_ver_info(struct ice_hw *hw) 
	 * (Combo Image Version High and Combo Image Version Low)

	 */

	if (boot_cfg_tlv_len < 2) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Invalid Boot Configuration Block TLV size.\n");

		ice_debug(hw, ICE_DBG_INIT, "Invalid Boot Configuration Block TLV size.\n");

		return ICE_ERR_INVAL_SIZE;

	}
@@ -542,14 +539,12 @@ static enum ice_status ice_discover_flash_size(struct ice_hw *hw) 
		status = ice_read_flat_nvm(hw, offset, &len, &data, false);

		if (status == ICE_ERR_AQ_ERROR &&

		    hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {

			ice_debug(hw, ICE_DBG_NVM,

				  "%s: New upper bound of %u bytes\n",

			ice_debug(hw, ICE_DBG_NVM, "%s: New upper bound of %u bytes\n",

				  __func__, offset);

			status = 0;

			max_size = offset;

		} else if (!status) {

			ice_debug(hw, ICE_DBG_NVM,

				  "%s: New lower bound of %u bytes\n",

			ice_debug(hw, ICE_DBG_NVM, "%s: New lower bound of %u bytes\n",

				  __func__, offset);

			min_size = offset;

		} else {
@@ -558,8 +553,7 @@ static enum ice_status ice_discover_flash_size(struct ice_hw *hw) 
		}

	}



	ice_debug(hw, ICE_DBG_NVM,

		  "Predicted flash size is %u bytes\n", max_size);

	ice_debug(hw, ICE_DBG_NVM, "Predicted flash size is %u bytes\n", max_size);



	hw->nvm.flash_size = max_size;
@@ -600,15 +594,13 @@ enum ice_status ice_init_nvm(struct ice_hw *hw) 
	} else {

		/* Blank programming mode */

		nvm->blank_nvm_mode = true;

		ice_debug(hw, ICE_DBG_NVM,

			  "NVM init error: unsupported blank mode.\n");

		ice_debug(hw, ICE_DBG_NVM, "NVM init error: unsupported blank mode.\n");

		return ICE_ERR_NVM_BLANK_MODE;

	}



	status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);

	if (status) {

		ice_debug(hw, ICE_DBG_INIT,

			  "Failed to read DEV starter version.\n");

		ice_debug(hw, ICE_DBG_INIT, "Failed to read DEV starter version.\n");

		return status;

	}

	nvm->major_ver = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
@@ -629,8 +621,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw) 


	status = ice_discover_flash_size(hw);

	if (status) {

		ice_debug(hw, ICE_DBG_NVM,

			  "NVM init error: failed to discover flash size.\n");

		ice_debug(hw, ICE_DBG_NVM, "NVM init error: failed to discover flash size.\n");

		return status;

	}

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