Commit 922430dd authored by Gwan-gyeong Mun's avatar Gwan-gyeong Mun Committed by Ville Syrjälä
Browse files

drm/i915: Add new GMP register size for GEN11 



According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses Uma's review comments.

v9: Add WARN_ON() when buffer size if larger than register size. [Ville]

Signed-off-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190919195311.13972-7-gwan-gyeong.mun@intel.com
parent 9d1bb6f0

drivers/gpu/drm/i915/display/intel_hdmi.c

+10 −2
Original line number Diff line number Diff line
@@ -189,13 +189,19 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, 
	}

}



static int hsw_dip_data_size(unsigned int type)

static int hsw_dip_data_size(struct drm_i915_private *dev_priv,

			     unsigned int type)

{

	switch (type) {

	case DP_SDP_VSC:

		return VIDEO_DIP_VSC_DATA_SIZE;

	case DP_SDP_PPS:

		return VIDEO_DIP_PPS_DATA_SIZE;

	case HDMI_PACKET_TYPE_GAMUT_METADATA:

		if (INTEL_GEN(dev_priv) >= 11)

			return VIDEO_DIP_GMP_DATA_SIZE;

		else

			return VIDEO_DIP_DATA_SIZE;

	default:

		return VIDEO_DIP_DATA_SIZE;

	}
@@ -514,7 +520,9 @@ static void hsw_write_infoframe(struct intel_encoder *encoder, 
	int i;

	u32 val = I915_READ(ctl_reg);



	data_size = hsw_dip_data_size(type);

	data_size = hsw_dip_data_size(dev_priv, type);



	WARN_ON(len > data_size);



	val &= ~hsw_infoframe_enable(type);

	I915_WRITE(ctl_reg, val);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4692,6 +4692,7 @@ enum { 
 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte

 * of the infoframe structure specified by CEA-861. */

#define   VIDEO_DIP_DATA_SIZE	32

#define   VIDEO_DIP_GMP_DATA_SIZE	36

#define   VIDEO_DIP_VSC_DATA_SIZE	36

#define   VIDEO_DIP_PPS_DATA_SIZE	132

#define VIDEO_DIP_CTL		_MMIO(0x61170)

CRA Git | Maintained and supported by SUSTech CRA and CCSE