Commit 9219a3b9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (37 commits)
  MIPS: Only write c0_framemask on CPUs which have this register.
  MIPS: Alchemy: new userspace suspend interface for development boards.
  MIPS: Alchemy: dbdma suspend/resume support.
  MIPS: Alchemy: Fix up PM code on Au1550/Au1200
  MIPS: Alchemy: move calc_clock function.
  MIPS: Alchemy: RTC counter clocksource / clockevent support.
  MIPS: make cp0 counter clocksource/event usable as fallback.
  MIPS: Alchemy: remove cpu_table.
  MIPS: Alchemy: remove get/set_au1x00_lcd_clock().
  MIPS: Print irq handler description
  MIPS: Alchemy: pb1200: update CPLD cascade irq handler.
  MIPS: Alchemy: update core interrupt code.
  MIPS: Alchemy: move commandline mangling out of common code
  MIPS: Alchemy: devboards: consolidate files
  MIPS: Alchemy: Move development board code to common subdirectory
  MIPS: Add Cavium OCTEON to arch/mips/Kconfig
  MIPS: Add defconfig for Cavium OCTEON.
  MIPS: Adjust the dma-common.c platform hooks.
  MIPS: Add Cavium OCTEON slot into proper tlb category.
  MIPS:  Compute branch returns for Cavium OCTEON specific branch instructions.
  ...
parents 23ead729 cde15b59

arch/mips/Kconfig

+69 −2
Original line number Diff line number Diff line
@@ -595,6 +595,44 @@ config WR_PPMC 
	  This enables support for the Wind River MIPS32 4KC PPMC evaluation

	  board, which is based on GT64120 bridge chip.



config CAVIUM_OCTEON_SIMULATOR

	bool "Support for the Cavium Networks Octeon Simulator"

	select CEVT_R4K

	select 64BIT_PHYS_ADDR

	select DMA_COHERENT

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select CPU_CAVIUM_OCTEON

	help

	  The Octeon simulator is software performance model of the Cavium

	  Octeon Processor. It supports simulating Octeon processors on x86

	  hardware.



config CAVIUM_OCTEON_REFERENCE_BOARD

	bool "Support for the Cavium Networks Octeon reference board"

	select CEVT_R4K

	select 64BIT_PHYS_ADDR

	select DMA_COHERENT

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_HAS_EARLY_PRINTK

	select CPU_CAVIUM_OCTEON

	select SWAP_IO_SPACE

	help

	  This option supports all of the Octeon reference boards from Cavium

	  Networks. It builds a kernel that dynamically determines the Octeon

	  CPU type and supports all known board reference implementations.

	  Some of the supported boards are:

		EBT3000

		EBH3000

		EBH3100

		Thunder

		Kodama

		Hikari

	  Say Y here for most Octeon reference boards.



endchoice



source "arch/mips/alchemy/Kconfig"
@@ -607,6 +645,7 @@ source "arch/mips/sgi-ip27/Kconfig" 
source "arch/mips/sibyte/Kconfig"

source "arch/mips/txx9/Kconfig"

source "arch/mips/vr41xx/Kconfig"

source "arch/mips/cavium-octeon/Kconfig"



endmenu
@@ -682,7 +721,11 @@ config CEVT_DS1287 
config CEVT_GT641XX

	bool



config CEVT_R4K_LIB

	bool



config CEVT_R4K

	select CEVT_R4K_LIB

	bool



config CEVT_SB1250
@@ -697,7 +740,11 @@ config CSRC_BCM1480 
config CSRC_IOASIC

	bool



config CSRC_R4K_LIB

	bool



config CSRC_R4K

	select CSRC_R4K_LIB

	bool



config CSRC_SB1250
@@ -835,6 +882,9 @@ config IRQ_GT641XX 
config IRQ_GIC

	bool



config IRQ_CPU_OCTEON

	bool



config MIPS_BOARDS_GEN

	bool
@@ -924,7 +974,7 @@ config BOOT_ELF32 
config MIPS_L1_CACHE_SHIFT

	int

	default "4" if MACH_DECSTATION || MIKROTIK_RB532

	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM

	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON

	default "4" if PMC_MSP4200_EVAL

	default "5"
@@ -1185,6 +1235,23 @@ config CPU_SB1 
	select CPU_SUPPORTS_HIGHMEM

	select WEAK_ORDERING



config CPU_CAVIUM_OCTEON

	bool "Cavium Octeon processor"

	select IRQ_CPU

	select IRQ_CPU_OCTEON

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_SMP

	select NR_CPUS_DEFAULT_16

	select WEAK_ORDERING

	select WEAK_REORDERING_BEYOND_LLSC

	select CPU_SUPPORTS_HIGHMEM

	help

	  The Cavium Octeon processor is a highly integrated chip containing

	  many ethernet hardware widgets for networking tasks. The processor

	  can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.

	  Full details can be found at http://www.caviumnetworks.com.



endchoice



config SYS_HAS_CPU_LOONGSON2
@@ -1285,7 +1352,7 @@ config CPU_MIPSR1 


config CPU_MIPSR2

	bool

	default y if CPU_MIPS32_R2 || CPU_MIPS64_R2

	default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON



config SYS_SUPPORTS_32BIT_KERNEL

	bool

arch/mips/Makefile

+28 −12
Original line number Diff line number Diff line
@@ -144,6 +144,10 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ 
cflags-$(CONFIG_CPU_R8000)	+= -march=r8000 -Wa,--trap

cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=r8000) \

			-Wa,--trap

cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap

ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))

cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon

endif



cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)

cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)
@@ -184,84 +188,84 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 
#

# AMD Alchemy Pb1000 eval board

#

libs-$(CONFIG_MIPS_PB1000)	+= arch/mips/alchemy/pb1000/

core-$(CONFIG_MIPS_PB1000)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_PB1000)	+= -I$(srctree)/arch/mips/include/asm/mach-pb1x00

load-$(CONFIG_MIPS_PB1000)	+= 0xffffffff80100000



#

# AMD Alchemy Pb1100 eval board

#

libs-$(CONFIG_MIPS_PB1100)	+= arch/mips/alchemy/pb1100/

core-$(CONFIG_MIPS_PB1100)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_PB1100)	+= -I$(srctree)/arch/mips/include/asm/mach-pb1x00

load-$(CONFIG_MIPS_PB1100)	+= 0xffffffff80100000



#

# AMD Alchemy Pb1500 eval board

#

libs-$(CONFIG_MIPS_PB1500)	+= arch/mips/alchemy/pb1500/

core-$(CONFIG_MIPS_PB1500)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_PB1500)	+= -I$(srctree)/arch/mips/include/asm/mach-pb1x00

load-$(CONFIG_MIPS_PB1500)	+= 0xffffffff80100000



#

# AMD Alchemy Pb1550 eval board

#

libs-$(CONFIG_MIPS_PB1550)	+= arch/mips/alchemy/pb1550/

core-$(CONFIG_MIPS_PB1550)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_PB1550)	+= -I$(srctree)/arch/mips/include/asm/mach-pb1x00

load-$(CONFIG_MIPS_PB1550)	+= 0xffffffff80100000



#

# AMD Alchemy Pb1200 eval board

#

libs-$(CONFIG_MIPS_PB1200)	+= arch/mips/alchemy/pb1200/

core-$(CONFIG_MIPS_PB1200)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_PB1200)	+= -I$(srctree)/arch/mips/include/asm/mach-pb1x00

load-$(CONFIG_MIPS_PB1200)	+= 0xffffffff80100000



#

# AMD Alchemy Db1000 eval board

#

libs-$(CONFIG_MIPS_DB1000)	+= arch/mips/alchemy/db1x00/

core-$(CONFIG_MIPS_DB1000)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_DB1000)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00

load-$(CONFIG_MIPS_DB1000)	+= 0xffffffff80100000



#

# AMD Alchemy Db1100 eval board

#

libs-$(CONFIG_MIPS_DB1100)	+= arch/mips/alchemy/db1x00/

core-$(CONFIG_MIPS_DB1100)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_DB1100)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00

load-$(CONFIG_MIPS_DB1100)	+= 0xffffffff80100000



#

# AMD Alchemy Db1500 eval board

#

libs-$(CONFIG_MIPS_DB1500)	+= arch/mips/alchemy/db1x00/

core-$(CONFIG_MIPS_DB1500)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_DB1500)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00

load-$(CONFIG_MIPS_DB1500)	+= 0xffffffff80100000



#

# AMD Alchemy Db1550 eval board

#

libs-$(CONFIG_MIPS_DB1550)	+= arch/mips/alchemy/db1x00/

core-$(CONFIG_MIPS_DB1550)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_DB1550)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00

load-$(CONFIG_MIPS_DB1550)	+= 0xffffffff80100000



#

# AMD Alchemy Db1200 eval board

#

libs-$(CONFIG_MIPS_DB1200)	+= arch/mips/alchemy/pb1200/

core-$(CONFIG_MIPS_DB1200)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_DB1200)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00

load-$(CONFIG_MIPS_DB1200)	+= 0xffffffff80100000



#

# AMD Alchemy Bosporus eval board

#

libs-$(CONFIG_MIPS_BOSPORUS)	+= arch/mips/alchemy/db1x00/

core-$(CONFIG_MIPS_BOSPORUS)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_BOSPORUS)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00

load-$(CONFIG_MIPS_BOSPORUS)	+= 0xffffffff80100000



#

# AMD Alchemy Mirage eval board

#

libs-$(CONFIG_MIPS_MIRAGE)	+= arch/mips/alchemy/db1x00/

core-$(CONFIG_MIPS_MIRAGE)	+= arch/mips/alchemy/devboards/

cflags-$(CONFIG_MIPS_MIRAGE)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00

load-$(CONFIG_MIPS_MIRAGE)	+= 0xffffffff80100000
@@ -586,6 +590,18 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/ 
core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/

core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/



#

# Cavium Octeon

#

core-$(CONFIG_CPU_CAVIUM_OCTEON)	+= arch/mips/cavium-octeon/

cflags-$(CONFIG_CPU_CAVIUM_OCTEON)	+= -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon

core-$(CONFIG_CPU_CAVIUM_OCTEON)	+= arch/mips/cavium-octeon/executive/

ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL

load-$(CONFIG_CPU_CAVIUM_OCTEON)	+= 0xffffffff84100000

else

load-$(CONFIG_CPU_CAVIUM_OCTEON) 	+= 0xffffffff81100000

endif



cflags-y			+= -I$(srctree)/arch/mips/include/asm/mach-generic

drivers-$(CONFIG_PCI)		+= arch/mips/pci/

arch/mips/alchemy/Kconfig

+3 −2
Original line number Diff line number Diff line
@@ -128,9 +128,10 @@ config SOC_AU1200 
config SOC_AU1X00

	bool

	select 64BIT_PHYS_ADDR

	select CEVT_R4K

	select CSRC_R4K

	select CEVT_R4K_LIB

	select CSRC_R4K_LIB

	select IRQ_CPU

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_APM_EMULATION

	select GENERIC_HARDIRQS_NO__DO_IRQ

arch/mips/alchemy/common/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -6,8 +6,8 @@ 
#



obj-y += prom.o irq.o puts.o time.o reset.o \

	au1xxx_irqmap.o clocks.o platform.o power.o setup.o \

	sleeper.o cputable.o dma.o dbdma.o gpio.o

	clocks.o platform.o power.o setup.o \

	sleeper.o dma.o dbdma.o gpio.o



obj-$(CONFIG_PCI)		+= pci.o

arch/mips/alchemy/common/au1xxx_irqmap.c

deleted100644 → 0
+0 −205
Original line number Diff line number Diff line 
/*

 * BRIEF MODULE DESCRIPTION

 *	Au1xxx processor specific IRQ tables

 *

 * Copyright 2004 Embedded Edge, LLC

 *	dan@embeddededge.com

 *

 *  This program is free software; you can redistribute	 it and/or modify it

 *  under  the terms of	 the GNU General  Public License as published by the

 *  Free Software Foundation;  either version 2 of the	License, or (at your

 *  option) any later version.

 *

 *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED

 *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF

 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN

 *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,

 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF

 *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON

 *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT

 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 *

 *  You should have received a copy of the  GNU General Public License along

 *  with this program; if not, write  to the Free Software Foundation, Inc.,

 *  675 Mass Ave, Cambridge, MA 02139, USA.

 */

#include <linux/init.h>

#include <linux/kernel.h>



#include <au1000.h>



/* The IC0 interrupt table.  This is processor, rather than

 * board dependent, so no reason to keep this info in the board

 * dependent files.

 *

 * Careful if you change match 2 request!

 * The interrupt handler is called directly from the low level dispatch code.

 */

struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {



#if defined(CONFIG_SOC_AU1000)

	{ AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },



#elif defined(CONFIG_SOC_AU1500)



	{ AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },

	{ AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },



#elif defined(CONFIG_SOC_AU1100)



	{ AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	/* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */

	{ AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },



#elif defined(CONFIG_SOC_AU1550)



	{ AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },

	{ AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },



#elif defined(CONFIG_SOC_AU1200)



	{ AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },

	{ AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 },

	{ AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },

	{ AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 },



#else

#error "Error: Unknown Alchemy SOC"

#endif



};



int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);

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