Merge tag 'v4.4-next-arm64' of https://github.com/mbgg/linux-mediatek into next/dt64 (9205a7ad) · Commits · 戴 / test

arch/arm64/boot/dts/mediatek/mt8173-evb.dts

+13 −0

Original line number	Diff line number	Diff line
		@@ -92,6 +92,13 @@
		};

		&pio {
		disp_pwm0_pins: disp_pwm0_pins {
		pins1 {
		pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
		output-low;
		};
		};

		mmc0_pins_default: mmc0default {
		pins_cmd_dat {
		pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
		@@ -190,6 +197,12 @@
		};
		};

		&pwm0 {
		pinctrl-names = "default";
		pinctrl-0 = <&disp_pwm0_pins>;
		status = "okay";
		};

		&pwrap {
		pmic: mt6397 {
		compatible = "mediatek,mt6397";

+32 −1

Original line number	Diff line number	Diff line
		@@ -95,7 +95,7 @@
		};

		psci {
		compatible = "arm,psci";
		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
		method = "smc";
		cpu_suspend = <0x84000001>;
		cpu_off = <0x84000002>;
		@@ -247,6 +247,15 @@
		reg = <0 0x10007000 0 0x100>;
		};

		timer: timer@10008000 {
		compatible = "mediatek,mt8173-timer",
		"mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x1000>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_CLK_13M>,
		<&topckgen CLK_TOP_RTC_SEL>;
		};

		pwrap: pwrap@1000d000 {
		compatible = "mediatek,mt8173-pwrap";
		reg = <0 0x1000d000 0 0x1000>;
		@@ -516,6 +525,28 @@
		#clock-cells = <1>;
		};

		pwm0: pwm@1401e000 {
		compatible = "mediatek,mt8173-disp-pwm",
		"mediatek,mt6595-disp-pwm";
		reg = <0 0x1401e000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&mmsys CLK_MM_DISP_PWM026M>,
		<&mmsys CLK_MM_DISP_PWM0MM>;
		clock-names = "main", "mm";
		status = "disabled";
		};

		pwm1: pwm@1401f000 {
		compatible = "mediatek,mt8173-disp-pwm",
		"mediatek,mt6595-disp-pwm";
		reg = <0 0x1401f000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&mmsys CLK_MM_DISP_PWM126M>,
		<&mmsys CLK_MM_DISP_PWM1MM>;
		clock-names = "main", "mm";
		status = "disabled";
		};

		imgsys: clock-controller@15000000 {
		compatible = "mediatek,mt8173-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;