Commit 91fab9d2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'tegra-for-4.17-clk' of... 

Merge tag 'tegra-for-4.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra

Pull tegra clk driver updates from Thierry Reding:

This contains preliminary work for the MBIST workaround implemented in
the Tegra PMC driver. There's also some fixes to various clocks for bugs
that went unnoticed for a long time.

* tag 'tegra-for-4.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Fix pll_u rate configuration
  clk: tegra: Specify VDE clock rate
  clk: tegra20: Correct PLL_C_OUT1 setup
  clk: tegra: Mark HCLK, SCLK and EMC as critical
  clk: tegra: MBIST work around for Tegra210
  clk: tegra: add fence_delay for clock registers
  clk: tegra: Add la clock for Tegra210
parents 7928b2cb c35b518f

drivers/clk/tegra/clk-emc.c

+1 −1
Original line number Diff line number Diff line
@@ -515,7 +515,7 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 


	init.name = "emc";

	init.ops = &tegra_clk_emc_ops;

	init.flags = 0;

	init.flags = CLK_IS_CRITICAL;

	init.parent_names = emc_parent_clk_names;

	init.num_parents = ARRAY_SIZE(emc_parent_clk_names);

drivers/clk/tegra/clk-pll.c

+2 −0
Original line number Diff line number Diff line
@@ -1151,6 +1151,8 @@ static const struct clk_ops tegra_clk_pllu_ops = { 
	.enable = clk_pllu_enable,

	.disable = clk_pll_disable,

	.recalc_rate = clk_pll_recalc_rate,

	.round_rate = clk_pll_round_rate,

	.set_rate = clk_pll_set_rate,

};



static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,

drivers/clk/tegra/clk-tegra-periph.c

+1 −1
Original line number Diff line number Diff line
@@ -830,7 +830,7 @@ static struct tegra_periph_init_data gate_clks[] = { 
	GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),

	GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),

	GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),

	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),

	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),

	GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),

	GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),

	GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),

drivers/clk/tegra/clk-tegra-super-gen4.c

+5 −3
Original line number Diff line number Diff line
@@ -125,7 +125,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base, 
		/* SCLK */

		dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);

		if (dt_clk) {

			clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,

			clk = clk_register_divider(NULL, "sclk", "sclk_mux",

						CLK_IS_CRITICAL,

						clk_base + SCLK_DIVIDER, 0, 8,

						0, &sysrate_lock);

			*dt_clk = clk;
@@ -137,7 +138,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base, 
			clk = tegra_clk_register_super_mux("sclk",

						gen_info->sclk_parents,

						gen_info->num_sclk_parents,

						CLK_SET_RATE_PARENT,

						CLK_SET_RATE_PARENT |

						CLK_IS_CRITICAL,

						clk_base + SCLK_BURST_POLICY,

						0, 4, 0, 0, NULL);

			*dt_clk = clk;
@@ -151,7 +153,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base, 
				   clk_base + SYSTEM_CLK_RATE, 4, 2, 0,

				   &sysrate_lock);

		clk = clk_register_gate(NULL, "hclk", "hclk_div",

				CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,

				CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

				clk_base + SYSTEM_CLK_RATE,

				7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);

		*dt_clk = clk;

drivers/clk/tegra/clk-tegra114.c

+2 −2
Original line number Diff line number Diff line
@@ -955,8 +955,7 @@ static void __init tegra114_pll_init(void __iomem *clk_base, 


	/* PLLM */

	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,

			     CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,

			     &pll_m_params, NULL);

			     CLK_SET_RATE_GATE, &pll_m_params, NULL);

	clks[TEGRA114_CLK_PLL_M] = clk;



	/* PLLM_OUT1 */
@@ -1190,6 +1189,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{ TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },

	{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },

	{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },

	{ TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },

	/* must be the last entry */

	{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },

};

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