Commit 91e4f1b6 authored by James Hogan's avatar James Hogan
Browse files

KVM: MIPS: Drop other CPU ASIDs on guest MMU changes 



When a guest TLB entry is replaced by TLBWI or TLBWR, we only invalidate
TLB entries on the local CPU. This doesn't work correctly on an SMP host
when the guest is migrated to a different physical CPU, as it could pick
up stale TLB mappings from the last time the vCPU ran on that physical
CPU.

Therefore invalidate both user and kernel host ASIDs on other CPUs,
which will cause new ASIDs to be generated when it next runs on those
CPUs.

We're careful only to do this if the TLB entry was already valid, and
only for the kernel ASID where the virtual address it mapped is outside
of the guest user address range.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Cc: <stable@vger.kernel.org> # 3.10.x-
parent d5888477

arch/mips/kvm/emulate.c

+53 −10
Original line number Diff line number Diff line
@@ -846,6 +846,47 @@ enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu) 
	return EMULATE_FAIL;

}



/**

 * kvm_mips_invalidate_guest_tlb() - Indicates a change in guest MMU map.

 * @vcpu:	VCPU with changed mappings.

 * @tlb:	TLB entry being removed.

 *

 * This is called to indicate a single change in guest MMU mappings, so that we

 * can arrange TLB flushes on this and other CPUs.

 */

static void kvm_mips_invalidate_guest_tlb(struct kvm_vcpu *vcpu,

					  struct kvm_mips_tlb *tlb)

{

	int cpu, i;

	bool user;



	/* No need to flush for entries which are already invalid */

	if (!((tlb->tlb_lo[0] | tlb->tlb_lo[1]) & ENTRYLO_V))

		return;

	/* User address space doesn't need flushing for KSeg2/3 changes */

	user = tlb->tlb_hi < KVM_GUEST_KSEG0;



	preempt_disable();



	/*

	 * Probe the shadow host TLB for the entry being overwritten, if one

	 * matches, invalidate it

	 */

	kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);



	/* Invalidate the whole ASID on other CPUs */

	cpu = smp_processor_id();

	for_each_possible_cpu(i) {

		if (i == cpu)

			continue;

		if (user)

			vcpu->arch.guest_user_asid[i] = 0;

		vcpu->arch.guest_kernel_asid[i] = 0;

	}



	preempt_enable();

}



/* Write Guest TLB Entry @ Index */

enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)

{
@@ -865,11 +906,8 @@ enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu) 
	}



	tlb = &vcpu->arch.guest_tlb[index];

	/*

	 * Probe the shadow host TLB for the entry being overwritten, if one

	 * matches, invalidate it

	 */

	kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);



	kvm_mips_invalidate_guest_tlb(vcpu, tlb);



	tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);

	tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
@@ -898,11 +936,7 @@ enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) 


	tlb = &vcpu->arch.guest_tlb[index];



	/*

	 * Probe the shadow host TLB for the entry being overwritten, if one

	 * matches, invalidate it

	 */

	kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);

	kvm_mips_invalidate_guest_tlb(vcpu, tlb);



	tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);

	tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
@@ -1026,6 +1060,7 @@ enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, 
	enum emulation_result er = EMULATE_DONE;

	u32 rt, rd, sel;

	unsigned long curr_pc;

	int cpu, i;



	/*

	 * Update PC and hold onto current PC in case there is
@@ -1135,8 +1170,16 @@ enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, 
							& KVM_ENTRYHI_ASID,

						nasid);



					preempt_disable();

					/* Blow away the shadow host TLBs */

					kvm_mips_flush_host_tlb(1);

					cpu = smp_processor_id();

					for_each_possible_cpu(i)

						if (i != cpu) {

							vcpu->arch.guest_user_asid[i] = 0;

							vcpu->arch.guest_kernel_asid[i] = 0;

						}

					preempt_enable();

				}

				kvm_write_c0_guest_entryhi(cop0,

							   vcpu->arch.gprs[rt]);

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