Commit 91d0ca3d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2020-09-27' of https://gitlab.freedesktop.org/drm/msm into drm-next 



* DSI support for sm8150/sm8250
* Support for per-process GPU pagetables (finally!) for a6xx.
  There are still some iommu/arm-smmu changes required to
  enable, without which it will fallback to the current single
  pgtable state.  The first part (ie. what doesn't depend on
  drm side patches) is queued up for v5.10[1].
* DisplayPort support.  Userspace DP compliance tool support
  is already merged in IGT[2]
* The usual assortment of smaller fixes/cleanups

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvqjuzH=Po_9EzzFsp2Xq3tqJUTKfsA2g09XY7_+6Ypfw@mail.gmail.com
parents 32e4d9df d1ea9149

Documentation/devicetree/bindings/display/msm/dsi.txt

+4 −2
Original line number Diff line number Diff line
@@ -90,6 +90,8 @@ Required properties: 
  * "qcom,dsi-phy-14nm-660"

  * "qcom,dsi-phy-10nm"

  * "qcom,dsi-phy-10nm-8998"

  * "qcom,dsi-phy-7nm"

  * "qcom,dsi-phy-7nm-8150"

- reg: Physical base address and length of the registers of PLL, PHY. Some

  revisions require the PHY regulator base address, whereas others require the

  PHY lane base address. See below for each PHY revision.
@@ -98,7 +100,7 @@ Required properties: 
  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

  For DSI 14nm and 10nm PHYs:

  For DSI 14nm, 10nm and 7nm PHYs:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_lane"
@@ -116,7 +118,7 @@ Required properties: 
- vcca-supply: phandle to vcca regulator device node

  For 14nm PHY:

- vcca-supply: phandle to vcca regulator device node

  For 10nm PHY:

  For 10nm and 7nm PHY:

- vdds-supply: phandle to vdds regulator device node



Optional properties:

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -8168,7 +8168,7 @@ static void compute_m_n(unsigned int m, unsigned int n, 
	 * which the devices expect also in synchronous clock mode.

	 */

	if (constant_n)

		*ret_n = 0x8000;

		*ret_n = DP_LINK_CONSTANT_N_VALUE;

	else

		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
































drivers/gpu/drm/msm/Kconfig



+18
−1






























Original line number
Diff line number
Diff line







@@ -6,8 +6,8 @@ config DRM_MSM







	depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST)









	depends on OF && COMMON_CLK









	depends on MMU









	depends on INTERCONNECT || !INTERCONNECT









	depends on QCOM_OCMEM || QCOM_OCMEM=n









	select IOMMU_IO_PGTABLE









	select QCOM_MDT_LOADER if ARCH_QCOM









	select REGULATOR









	select DRM_KMS_HELPER








@@ -57,6 +57,15 @@ config DRM_MSM_HDMI_HDCP







	help









	  Choose this option to enable HDCP state machine



















config DRM_MSM_DP









	bool "Enable DisplayPort support in MSM DRM driver"









	depends on DRM_MSM









	default y









	help









	  Compile in support for DP driver in MSM DRM driver. DP external









	  display support is enabled through this config option. It can









	  be primary or secondary display on device.



















config DRM_MSM_DSI









	bool "Enable DSI support in MSM DRM driver"









	depends on DRM_MSM








@@ -110,3 +119,11 @@ config DRM_MSM_DSI_10NM_PHY







	default y









	help









	  Choose this option if DSI PHY on SDM845 is used on the platform.



















config DRM_MSM_DSI_7NM_PHY









	bool "Enable DSI 7nm PHY driver in MSM DRM (used by SM8150/SM8250)"









	depends on DRM_MSM_DSI









	default y









	help









	  Choose this option if DSI PHY on SM8150/SM8250 is used on the









	  platform.
























drivers/gpu/drm/msm/Makefile



+17
−1






























Original line number
Diff line number
Diff line







@@ -2,6 +2,7 @@







ccflags-y := -I $(srctree)/$(src)









ccflags-y += -I $(srctree)/$(src)/disp/dpu1









ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi









ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp



















msm-y := \









	adreno/adreno_device.o \








@@ -95,10 +96,23 @@ msm-y := \







	msm_gpu_tracepoints.o \









	msm_gpummu.o



















msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o









msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \









	dp/dp_debug.o



















msm-$(CONFIG_DRM_MSM_GPU_STATE)	+= adreno/a6xx_gpu_state.o



















msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \









	dp/dp_catalog.o \









	dp/dp_ctrl.o \









	dp/dp_display.o \









	dp/dp_drm.o \









	dp/dp_hpd.o \









	dp/dp_link.o \









	dp/dp_panel.o \









	dp/dp_parser.o \









	dp/dp_power.o \









	dp/dp_audio.o



















msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o









msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o









msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o








@@ -119,6 +133,7 @@ msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o







msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o









msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o









msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o









msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o



















ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)









msm-y += dsi/pll/dsi_pll.o








@@ -126,6 +141,7 @@ msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o







msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o









msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o









msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o









msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/pll/dsi_pll_7nm.o









endif



















obj-$(CONFIG_DRM_MSM)	+= msm.o
























drivers/gpu/drm/msm/adreno/a2xx_gpu.c



+50
−15






























Original line number
Diff line number
Diff line







@@ -10,6 +10,48 @@ extern bool hang_debug;







static void a2xx_dump(struct msm_gpu *gpu);









static bool a2xx_idle(struct msm_gpu *gpu);



















static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)









{









	struct msm_drm_private *priv = gpu->dev->dev_private;









	struct msm_ringbuffer *ring = submit->ring;









	unsigned int i;



















	for (i = 0; i < submit->nr_cmds; i++) {









		switch (submit->cmd[i].type) {









		case MSM_SUBMIT_CMD_IB_TARGET_BUF:









			/* ignore IB-targets */









			break;









		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:









			/* ignore if there has not been a ctx switch: */









			if (priv->lastctx == submit->queue->ctx)









				break;









			fallthrough;









		case MSM_SUBMIT_CMD_BUF:









			OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);









			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));









			OUT_RING(ring, submit->cmd[i].size);









			OUT_PKT2(ring);









			break;









		}









	}



















	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);









	OUT_RING(ring, submit->seqno);



















	/* wait for idle before cache flush/interrupt */









	OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);









	OUT_RING(ring, 0x00000000);



















	OUT_PKT3(ring, CP_EVENT_WRITE, 3);









	OUT_RING(ring, CACHE_FLUSH_TS);









	OUT_RING(ring, rbmemptr(ring, fence));









	OUT_RING(ring, submit->seqno);









	OUT_PKT3(ring, CP_INTERRUPT, 1);









	OUT_RING(ring, 0x80000000);



















	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);









}



















static bool a2xx_me_init(struct msm_gpu *gpu)









{









	struct msm_ringbuffer *ring = gpu->rb[0];








@@ -53,7 +95,7 @@ static bool a2xx_me_init(struct msm_gpu *gpu)







	OUT_PKT3(ring, CP_SET_PROTECTED_MODE, 1);









	OUT_RING(ring, 1);



















	gpu->funcs->flush(gpu, ring);









	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);









	return a2xx_idle(gpu);









}


















@@ -421,16 +463,11 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)







	return aspace;









}



















/* Register offset defines for A2XX - copy of A3XX */









static const unsigned int a2xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {









	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),









	REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),









	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),









	REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),









	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),









	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),









	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),









};









static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)









{









	ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);









	return ring->memptrs->rptr;









}



















static const struct adreno_gpu_funcs funcs = {









	.base = {








@@ -439,8 +476,7 @@ static const struct adreno_gpu_funcs funcs = {







		.pm_suspend = msm_gpu_pm_suspend,









		.pm_resume = msm_gpu_pm_resume,









		.recover = a2xx_recover,









		.submit = adreno_submit,









		.flush = adreno_flush,









		.submit = a2xx_submit,









		.active_ring = adreno_active_ring,









		.irq = a2xx_irq,









		.destroy = a2xx_destroy,








@@ -450,6 +486,7 @@ static const struct adreno_gpu_funcs funcs = {







		.gpu_state_get = a2xx_gpu_state_get,









		.gpu_state_put = adreno_gpu_state_put,









		.create_address_space = a2xx_create_address_space,









		.get_rptr = a2xx_get_rptr,









	},









};


















@@ -491,8 +528,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)







	else









		adreno_gpu->registers = a220_registers;



















	adreno_gpu->reg_offsets = a2xx_register_offsets;



















	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);









	if (ret)









		goto fail;








































































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