Commit 91c1ead6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-5.3' of git://people.freedesktop.org/~agd5f/linux into drm-next 

New stuff for 5.3:
- Add new thermal sensors for vega asics
- Various RAS fixes
- Add sysfs interface for memory interface utilization
- Use HMM rather than mmu notifier for user pages
- Expose xgmi topology via kfd
- SR-IOV fixes
- Fixes for manual driver reload
- Add unique identifier for vega asics
- Clean up user fence handling with UVD/VCE/VCN blocks
- Convert DC to use core bpc attribute rather than a custom one
- Add GWS support for KFD
- Vega powerplay improvements
- Add CRC support for DCE 12
- SR-IOV support for new security policy
- Various cleanups

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190529220944.14464-1-alexander.deucher@amd.com
parents 14ee642c cf401e28

Documentation/gpu/amdgpu.rst

+20 −0
Original line number Diff line number Diff line
@@ -70,6 +70,26 @@ Interrupt Handling 
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

   :internal:



AMDGPU XGMI Support

===================



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

   :doc: AMDGPU XGMI Support



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

   :internal:



AMDGPU RAS debugfs control interface

====================================



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   :doc: AMDGPU RAS debugfs control interface





.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   :internal:





GPU Power/Thermal Controls and Monitoring

=========================================

drivers/gpu/drm/amd/amdgpu/Kconfig

+4 −3
Original line number Diff line number Diff line
@@ -27,10 +27,11 @@ config DRM_AMDGPU_CIK 
config DRM_AMDGPU_USERPTR

	bool "Always enable userptr write support"

	depends on DRM_AMDGPU

	select MMU_NOTIFIER

	depends on ARCH_HAS_HMM

	select HMM_MIRROR

	help

	  This option selects CONFIG_MMU_NOTIFIER if it isn't already

	  selected to enabled full userptr support.

	  This option selects CONFIG_HMM and CONFIG_HMM_MIRROR if it

	  isn't already selected to enabled full userptr support.



config DRM_AMDGPU_GART_DEBUGFS

	bool "Allow GART access through debugfs"

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \

	amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \

	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \

	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_dma_buf.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \

	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
@@ -173,7 +173,7 @@ endif 
amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o

amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o

amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o

amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o

amdgpu-$(CONFIG_HMM_MIRROR) += amdgpu_mn.o



include $(FULL_AMD_PATH)/powerplay/Makefile

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+28 −1
Original line number Diff line number Diff line
@@ -118,7 +118,6 @@ extern int amdgpu_disp_priority; 
extern int amdgpu_hw_i2c;

extern int amdgpu_pcie_gen2;

extern int amdgpu_msi;

extern int amdgpu_lockup_timeout;

extern int amdgpu_dpm;

extern int amdgpu_fw_load_type;

extern int amdgpu_aspm;
@@ -211,6 +210,7 @@ struct amdgpu_irq_src; 
struct amdgpu_fpriv;

struct amdgpu_bo_va_mapping;

struct amdgpu_atif;

struct kfd_vm_fault_info;



enum amdgpu_cp_irq {

	AMDGPU_CP_IRQ_GFX_EOP = 0,
@@ -415,6 +415,7 @@ struct amdgpu_fpriv { 
};



int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);

int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size, struct amdgpu_ib *ib);
@@ -558,6 +559,8 @@ struct amdgpu_asic_funcs { 
			       uint64_t *count1);

	/* do we need to reset the asic at init time (e.g., kexec) */

	bool (*need_reset_on_init)(struct amdgpu_device *adev);

	/* PCIe replay counter */

	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);

};



/*
@@ -639,6 +642,11 @@ struct nbio_hdp_flush_reg { 
	u32 ref_and_mask_sdma1;

};



struct amdgpu_mmio_remap {

	u32 reg_offset;

	resource_size_t bus_addr;

};



struct amdgpu_nbio_funcs {

	const struct nbio_hdp_flush_reg *hdp_flush_reg;

	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
@@ -666,6 +674,7 @@ struct amdgpu_nbio_funcs { 
	void (*ih_control)(struct amdgpu_device *adev);

	void (*init_registers)(struct amdgpu_device *adev);

	void (*detect_hw_virt)(struct amdgpu_device *adev);

	void (*remap_hdp_registers)(struct amdgpu_device *adev);

};



struct amdgpu_df_funcs {
@@ -680,6 +689,12 @@ struct amdgpu_df_funcs { 
				      u32 *flags);

	void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,

					    bool enable);

	int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,

					 int is_enable);

	int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,

					 int is_disable);

	void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,

					 uint64_t *count);

};

/* Define the HW IP blocks will be used in driver , add more if necessary */

enum amd_hw_ip_block_type {
@@ -764,6 +779,7 @@ struct amdgpu_device { 
	void __iomem			*rmmio;

	/* protects concurrent MM_INDEX/DATA based register access */

	spinlock_t mmio_idx_lock;

	struct amdgpu_mmio_remap        rmmio_remap;

	/* protects concurrent SMC based register access */

	spinlock_t smc_idx_lock;

	amdgpu_rreg_t			smc_rreg;
@@ -936,6 +952,13 @@ struct amdgpu_device { 
	struct work_struct		xgmi_reset_work;



	bool                            in_baco_reset;



	long				gfx_timeout;

	long				sdma_timeout;

	long				video_timeout;

	long				compute_timeout;



	uint64_t			unique_id;

};



static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1065,6 +1088,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))

#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))

#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))

#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))



/* Common functions */

bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
@@ -1081,6 +1105,9 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 
					     const u32 array_size);



bool amdgpu_device_is_px(struct drm_device *dev);

bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,

				      struct amdgpu_device *peer_adev);



/* atpx handler */

#if defined(CONFIG_VGA_SWITCHEROO)

void amdgpu_register_atpx_handler(void);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+68 −2
Original line number Diff line number Diff line
@@ -25,8 +25,10 @@ 
#include <drm/drmP.h>

#include "amdgpu.h"

#include "amdgpu_gfx.h"

#include "amdgpu_dma_buf.h"

#include <linux/module.h>

#include <linux/dma-buf.h>

#include "amdgpu_xgmi.h"



static const unsigned int compute_vmid_bitmap = 0xFF00;
@@ -148,7 +150,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
		};



		/* this is going to have a few of the MSBs set that we need to

		 * clear */

		 * clear

		 */

		bitmap_complement(gpu_resources.queue_bitmap,

				  adev->gfx.mec.queue_bitmap,

				  KGD_MAX_QUEUES);
@@ -162,7 +165,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
				  gpu_resources.queue_bitmap);



		/* According to linux/bitmap.h we shouldn't use bitmap_clear if

		 * nbits is not compile time constant */

		 * nbits is not compile time constant

		 */

		last_valid_bit = 1 /* only first MEC can have compute queues */

				* adev->gfx.mec.num_pipe_per_mec

				* adev->gfx.mec.num_queue_per_pipe;
@@ -335,6 +339,40 @@ void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) 
	amdgpu_bo_unref(&(bo));

}



int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,

				void **mem_obj)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	struct amdgpu_bo *bo = NULL;

	struct amdgpu_bo_param bp;

	int r;



	memset(&bp, 0, sizeof(bp));

	bp.size = size;

	bp.byte_align = 1;

	bp.domain = AMDGPU_GEM_DOMAIN_GWS;

	bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;

	bp.type = ttm_bo_type_device;

	bp.resv = NULL;



	r = amdgpu_bo_create(adev, &bp, &bo);

	if (r) {

		dev_err(adev->dev,

			"failed to allocate gws BO for amdkfd (%d)\n", r);

		return r;

	}



	*mem_obj = bo;

	return 0;

}



void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)

{

	struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;



	amdgpu_bo_unref(&bo);

}



uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,

				      enum kgd_engine_type type)

{
@@ -518,6 +556,34 @@ uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) 


	return adev->gmc.xgmi.hive_id;

}

uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)

{

	struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;

	struct amdgpu_device *adev = (struct amdgpu_device *)dst;

	int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);



	if (ret < 0) {

		DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",

			adev->gmc.xgmi.physical_node_id,

			peer_adev->gmc.xgmi.physical_node_id, ret);

		ret = 0;

	}

	return  (uint8_t)ret;

}



uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;



	return adev->rmmio_remap.bus_addr;

}



uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;



	return adev->gds.gws_size;

}



int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,

				uint32_t vmid, uint64_t gpu_addr,

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