Commit 91b440ed authored Aug 10, 2020 by Guillaume Tucker Committed by Krzysztof Kozlowski Aug 17, 2020

ARM: dts: exynos: add prefetch properties for L2C-310 cache

Add the devicetree properties to enable instruction and data prefetch
on exynos4210 and exynos4412 which use the L2C-310 cache. No other
Exynos chip appears to be using this L2 cache hardware.

This follows the default bits being set in the l2c_aux_val register
for the Exynos platform, which can now be cleared as a result.

Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

parent a084c9d2

arch/arm/boot/dts/exynos4210.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -102,6 +102,8 @@
		reg = <0x10502000 0x1000>;
		cache-unified;
		cache-level = <2>;
		prefetch-data = <1>;
		prefetch-instr = <1>;
		arm,tag-latency = <2 2 1>;
		arm,data-latency = <2 2 1>;
		};

arch/arm/boot/dts/exynos4412.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -218,6 +218,8 @@
		reg = <0x10502000 0x1000>;
		cache-unified;
		cache-level = <2>;
		prefetch-data = <1>;
		prefetch-instr = <1>;
		arm,tag-latency = <2 2 1>;
		arm,data-latency = <3 2 1>;
		arm,double-linefill = <1>;

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