can: flexcan: add ECC initialization for LX2160A (91a22bfe) · Commits · 戴 / test

After double check with Layerscape CAN owner (Pankaj Bansal), confirm that LX2160A indeed supports ECC feature, so correct the feature table. For SoCs with ECC supported, even use FLEXCAN_QUIRK_DISABLE_MECR quirk to disable non-correctable errors interrupt and freeze mode, had better use FLEXCAN_QUIRK_SUPPORT_ECC quirk to initialize all memory. Fixes: ("can: flexcan: add lx2160ar1 support") Cc: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by:

Joakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20201020155402.30318-5-qiangqing.zhang@nxp.com Signed-off-by:

Marc Kleine-Budde <mkl@pengutronix.de>

drivers/net/can/flexcan.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -217,7 +217,7 @@
		* MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes
		* VF610 FlexCAN3 ? no yes no yes yes? no
		* LS1021A FlexCAN2 03.00.04.00 no yes no no yes no
		* LX2160A FlexCAN3 03.00.23.00 no yes no no yes yes
		* LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes
		*
		* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
		*/
		@@ -411,7 +411,8 @@ static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
		static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
		.quirks = FLEXCAN_QUIRK_DISABLE_RXFG \| FLEXCAN_QUIRK_ENABLE_EACEN_RRS \|
		FLEXCAN_QUIRK_DISABLE_MECR \| FLEXCAN_QUIRK_BROKEN_PERR_STATE \|
		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP \| FLEXCAN_QUIRK_SUPPORT_FD,
		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP \| FLEXCAN_QUIRK_SUPPORT_FD \|
		FLEXCAN_QUIRK_SUPPORT_ECC,
		};

		static const struct can_bittiming_const flexcan_bittiming_const = {

Admin message