Commit 919f9abb authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Netlogic: move cpu_ready array to boot area 



Move the nlm_cpu_ready[] array used by the cpu wakeup code to the
boot area, along with rest of the boot parameter code.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5425/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 53c83219

arch/mips/include/asm/netlogic/common.h

+6 −0
Original line number Diff line number Diff line
@@ -39,11 +39,17 @@ 
 * Common SMP definitions

 */

#define RESET_VEC_PHYS		0x1fc00000

#define RESET_VEC_SIZE		8192		/* 8KB reset code and data */

#define RESET_DATA_PHYS		(RESET_VEC_PHYS + (1<<10))



/* Offsets of parameters in the RESET_DATA_PHYS area */

#define BOOT_THREAD_MODE	0

#define BOOT_NMI_LOCK		4

#define BOOT_NMI_HANDLER	8



/* CPU ready flags for each CPU */

#define BOOT_CPU_READY		2048



#ifndef __ASSEMBLY__

#include <linux/cpumask.h>

#include <linux/spinlock.h>

arch/mips/netlogic/common/reset.S

+4 −2
Original line number Diff line number Diff line
@@ -216,8 +216,10 @@ EXPORT(nlm_boot_siblings) 
	ori	t1, ST0_KX

#endif

	mtc0	t1, CP0_STATUS

	/* mark CPU ready */

	PTR_LA	t1, nlm_cpu_ready



	/* mark CPU ready, careful here, previous mtcr trashed registers */

	li	t3, CKSEG1ADDR(RESET_DATA_PHYS)

	ADDIU	t1, t3, BOOT_CPU_READY

	sll	v1, v0, 2

	PTR_ADDU t1, v1

	li	t2, 1

arch/mips/netlogic/common/smp.c

+3 −3
Original line number Diff line number Diff line
@@ -145,7 +145,6 @@ void nlm_cpus_done(void) 
 * Boot all other cpus in the system, initialize them, and bring them into

 * the boot function

 */

int nlm_cpu_ready[NR_CPUS];

unsigned long nlm_next_gp;

unsigned long nlm_next_sp;

static cpumask_t phys_cpu_present_mask;
@@ -168,6 +167,7 @@ void __init nlm_smp_setup(void) 
{

	unsigned int boot_cpu;

	int num_cpus, i, ncore;

	volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);

	char buf[64];



	boot_cpu = hard_smp_processor_id();
@@ -181,10 +181,10 @@ void __init nlm_smp_setup(void) 
	num_cpus = 1;

	for (i = 0; i < NR_CPUS; i++) {

		/*

		 * nlm_cpu_ready array is not set for the boot_cpu,

		 * cpu_ready array is not set for the boot_cpu,

		 * it is only set for ASPs (see smpboot.S)

		 */

		if (nlm_cpu_ready[i]) {

		if (cpu_ready[i]) {

			cpumask_set_cpu(i, &phys_cpu_present_mask);

			__cpu_number_map[i] = num_cpus;

			__cpu_logical_map[num_cpus] = i;

arch/mips/netlogic/common/smpboot.S

+3 −2
Original line number Diff line number Diff line
@@ -109,8 +109,9 @@ NESTED(nlm_rmiboot_preboot, 16, sp) 
	andi	t2, t0, 0x3	/* thread num */

	sll	t0, 2		/* offset in cpu array */



	PTR_LA	t1, nlm_cpu_ready /* mark CPU ready */

	PTR_ADDU t1, t0

	li	t3, CKSEG1ADDR(RESET_DATA_PHYS)

	ADDIU	t1, t3, BOOT_CPU_READY

	ADDU	t1, t0

	li	t3, 1

	sw	t3, 0(t1)

arch/mips/netlogic/xlp/setup.c

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ void __init prom_init(void) 


	/* Update reset entry point with CPU init code */

	reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS);

	memset(reset_vec, 0, RESET_VEC_SIZE);

	memcpy(reset_vec, (void *)nlm_reset_entry,

			(nlm_reset_entry_end - nlm_reset_entry));

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