Merge branch 'linux-5.8' of git://github.com/skeggsb/linux into drm-next (918b73dc) · Commits · 戴 / test

drivers/gpu/drm/nouveau/Kbuild

+6 −4

Original line number	Original line	Diff line number	Diff line
			NOUVEAU_PATH ?= $(srctree)

	# SPDX-License-Identifier: MIT		# SPDX-License-Identifier: MIT
	ccflags-y += -I $(srctree)/$(src)/include		ccflags-y += -I $(NOUVEAU_PATH)/$(src)/include
	ccflags-y += -I $(srctree)/$(src)/include/nvkm		ccflags-y += -I $(NOUVEAU_PATH)/$(src)/include/nvkm
	ccflags-y += -I $(srctree)/$(src)/nvkm		ccflags-y += -I $(NOUVEAU_PATH)/$(src)/nvkm
	ccflags-y += -I $(srctree)/$(src)		ccflags-y += -I $(NOUVEAU_PATH)/$(src)

	# NVKM - HW resource manager		# NVKM - HW resource manager
	#- code also used by various userspace tools/tests		#- code also used by various userspace tools/tests

drivers/gpu/drm/nouveau/dispnv04/crtc.c

+10 −9

Original line number	Original line	Diff line number	Diff line
	@@ -605,15 +605,16 @@ static int
	nv_crtc_swap_fbs(struct drm_crtc crtc, struct drm_framebuffer old_fb)		nv_crtc_swap_fbs(struct drm_crtc crtc, struct drm_framebuffer old_fb)
	{		{
	struct nv04_display *disp = nv04_display(crtc->dev);		struct nv04_display *disp = nv04_display(crtc->dev);
	struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);		struct drm_framebuffer *fb = crtc->primary->fb;
			struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	int ret;		int ret;

	ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false);		ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, false);
	if (ret == 0) {		if (ret == 0) {
	if (disp->image[nv_crtc->index])		if (disp->image[nv_crtc->index])
	nouveau_bo_unpin(disp->image[nv_crtc->index]);		nouveau_bo_unpin(disp->image[nv_crtc->index]);
	nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]);		nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]);
	}		}

	return ret;		return ret;
	@@ -822,8 +823,8 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
	struct drm_device *dev = crtc->dev;		struct drm_device *dev = crtc->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];		struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
			struct nouveau_bo *nvbo;
	struct drm_framebuffer *drm_fb;		struct drm_framebuffer *drm_fb;
	struct nouveau_framebuffer *fb;
	int arb_burst, arb_lwm;		int arb_burst, arb_lwm;

	NV_DEBUG(drm, "index %d\n", nv_crtc->index);		NV_DEBUG(drm, "index %d\n", nv_crtc->index);
	@@ -839,13 +840,12 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
	*/		*/
	if (atomic) {		if (atomic) {
	drm_fb = passed_fb;		drm_fb = passed_fb;
	fb = nouveau_framebuffer(passed_fb);
	} else {		} else {
	drm_fb = crtc->primary->fb;		drm_fb = crtc->primary->fb;
	fb = nouveau_framebuffer(crtc->primary->fb);
	}		}

	nv_crtc->fb.offset = fb->nvbo->bo.offset;		nvbo = nouveau_gem_object(drm_fb->obj[0]);
			nv_crtc->fb.offset = nvbo->bo.offset;

	if (nv_crtc->lut.depth != drm_fb->format->depth) {		if (nv_crtc->lut.depth != drm_fb->format->depth) {
	nv_crtc->lut.depth = drm_fb->format->depth;		nv_crtc->lut.depth = drm_fb->format->depth;
	@@ -1143,8 +1143,9 @@ nv04_crtc_page_flip(struct drm_crtc crtc, struct drm_framebuffer fb,
	const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;		const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1;
	struct drm_device *dev = crtc->dev;		struct drm_device *dev = crtc->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);		struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->primary->fb)->nvbo;		struct drm_framebuffer *old_fb = crtc->primary->fb;
	struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo;		struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]);
			struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]);
	struct nv04_page_flip_state *s;		struct nv04_page_flip_state *s;
	struct nouveau_channel *chan;		struct nouveau_channel *chan;
	struct nouveau_cli *cli;		struct nouveau_cli *cli;

drivers/gpu/drm/nouveau/dispnv04/disp.c

+11 −10

Original line number	Original line	Diff line number	Diff line
	@@ -30,6 +30,7 @@
	#include "nouveau_encoder.h"		#include "nouveau_encoder.h"
	#include "nouveau_connector.h"		#include "nouveau_connector.h"
	#include "nouveau_bo.h"		#include "nouveau_bo.h"
			#include "nouveau_gem.h"

	#include <nvif/if0004.h>		#include <nvif/if0004.h>

	@@ -52,13 +53,13 @@ nv04_display_fini(struct drm_device *dev, bool suspend)

	/* Un-pin FB and cursors so they'll be evicted to system memory. */		/* Un-pin FB and cursors so they'll be evicted to system memory. */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	struct nouveau_framebuffer *nouveau_fb;		struct drm_framebuffer *fb = crtc->primary->fb;
			struct nouveau_bo *nvbo;

	nouveau_fb = nouveau_framebuffer(crtc->primary->fb);		if (!fb \|\| !fb->obj[0])
	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	continue;		continue;
			nvbo = nouveau_gem_object(fb->obj[0]);
	nouveau_bo_unpin(nouveau_fb->nvbo);		nouveau_bo_unpin(nvbo);
	}		}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	@@ -104,13 +105,13 @@ nv04_display_init(struct drm_device *dev, bool resume, bool runtime)

	/* Re-pin FB/cursors. */		/* Re-pin FB/cursors. */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	struct nouveau_framebuffer *nouveau_fb;		struct drm_framebuffer *fb = crtc->primary->fb;
			struct nouveau_bo *nvbo;

	nouveau_fb = nouveau_framebuffer(crtc->primary->fb);		if (!fb \|\| !fb->obj[0])
	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	continue;		continue;
			nvbo = nouveau_gem_object(fb->obj[0]);
	ret = nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM, true);		ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
	if (ret)		if (ret)
	NV_ERROR(drm, "Could not pin framebuffer\n");		NV_ERROR(drm, "Could not pin framebuffer\n");
	}		}

drivers/gpu/drm/nouveau/dispnv04/overlay.c

+12 −9

Original line number	Original line	Diff line number	Diff line
	@@ -31,6 +31,7 @@
	#include "nouveau_bo.h"		#include "nouveau_bo.h"
	#include "nouveau_connector.h"		#include "nouveau_connector.h"
	#include "nouveau_display.h"		#include "nouveau_display.h"
			#include "nouveau_gem.h"
	#include "nvreg.h"		#include "nvreg.h"
	#include "disp.h"		#include "disp.h"

	@@ -120,9 +121,9 @@ nv10_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	struct nvif_object *dev = &drm->client.device.object;		struct nvif_object *dev = &drm->client.device.object;
	struct nouveau_plane *nv_plane =		struct nouveau_plane *nv_plane =
	container_of(plane, struct nouveau_plane, base);		container_of(plane, struct nouveau_plane, base);
	struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	struct nouveau_bo *cur = nv_plane->cur;		struct nouveau_bo *cur = nv_plane->cur;
			struct nouveau_bo *nvbo;
	bool flip = nv_plane->flip;		bool flip = nv_plane->flip;
	int soff = NV_PCRTC0_SIZE * nv_crtc->index;		int soff = NV_PCRTC0_SIZE * nv_crtc->index;
	int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index;		int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index;
	@@ -140,17 +141,18 @@ nv10_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	if (ret)		if (ret)
	return ret;		return ret;

	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);		nvbo = nouveau_gem_object(fb->obj[0]);
			ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, false);
	if (ret)		if (ret)
	return ret;		return ret;

	nv_plane->cur = nv_fb->nvbo;		nv_plane->cur = nvbo;

	nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);		nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY);
	nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);		nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);

	nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0);		nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0);
	nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset);		nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nvbo->bo.offset);
	nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 \| src_w);		nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 \| src_w);
	nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 \| src_x);		nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 \| src_x);
	nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);		nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);
	@@ -172,7 +174,7 @@ nv10_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	if (format & NV_PVIDEO_FORMAT_PLANAR) {		if (format & NV_PVIDEO_FORMAT_PLANAR) {
	nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);		nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);
	nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),		nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),
	nv_fb->nvbo->bo.offset + fb->offsets[1]);		nvbo->bo.offset + fb->offsets[1]);
	}		}
	nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format \| fb->pitches[0]);		nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format \| fb->pitches[0]);
	nvif_wr32(dev, NV_PVIDEO_STOP, 0);		nvif_wr32(dev, NV_PVIDEO_STOP, 0);
	@@ -368,8 +370,8 @@ nv04_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object;		struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object;
	struct nouveau_plane *nv_plane =		struct nouveau_plane *nv_plane =
	container_of(plane, struct nouveau_plane, base);		container_of(plane, struct nouveau_plane, base);
	struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
	struct nouveau_bo *cur = nv_plane->cur;		struct nouveau_bo *cur = nv_plane->cur;
			struct nouveau_bo *nvbo;
	uint32_t overlay = 1;		uint32_t overlay = 1;
	int brightness = (nv_plane->brightness - 512) * 62 / 512;		int brightness = (nv_plane->brightness - 512) * 62 / 512;
	int ret, i;		int ret, i;
	@@ -384,11 +386,12 @@ nv04_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	if (ret)		if (ret)
	return ret;		return ret;

	ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false);		nvbo = nouveau_gem_object(fb->obj[0]);
			ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, false);
	if (ret)		if (ret)
	return ret;		return ret;

	nv_plane->cur = nv_fb->nvbo;		nv_plane->cur = nvbo;

	nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0);		nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0);
	nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0);		nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0);
	@@ -396,7 +399,7 @@ nv04_update_plane(struct drm_plane plane, struct drm_crtc crtc,

	for (i = 0; i < 2; i++) {		for (i = 0; i < 2; i++) {
	nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,		nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,
	nv_fb->nvbo->bo.offset);		nvbo->bo.offset);
	nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i,		nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i,
	fb->pitches[0]);		fb->pitches[0]);
	nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);		nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);

drivers/gpu/drm/nouveau/dispnv50/base507c.c

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -263,7 +263,8 @@ base507c_new_(const struct nv50_wndw_func func, const u32 format,
	struct nv50_disp_base_channel_dma_v0 args = {		struct nv50_disp_base_channel_dma_v0 args = {
	.head = head,		.head = head,
	};		};
	struct nv50_disp *disp = nv50_disp(drm->dev);		struct nouveau_display *disp = nouveau_display(drm->dev);
			struct nv50_disp *disp50 = nv50_disp(drm->dev);
	struct nv50_wndw *wndw;		struct nv50_wndw *wndw;
	int ret;		int ret;

	@@ -273,9 +274,9 @@ base507c_new_(const struct nv50_wndw_func func, const u32 format,
	if (*pwndw = wndw, ret)		if (*pwndw = wndw, ret)
	return ret;		return ret;

	ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,		ret = nv50_dmac_create(&drm->client.device, &disp->disp.object,
	&oclass, head, &args, sizeof(args),		&oclass, head, &args, sizeof(args),
	disp->sync->bo.offset, &wndw->wndw);		disp50->sync->bo.offset, &wndw->wndw);
	if (ret) {		if (ret) {
	NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret);		NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret);
	return ret;		return ret;

Admin message