Commit 915e1968 authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

ARM: dts: imx: Make tempmon node as child of anatop node 



i.MX6/7 SoCs' temperature sensor is inside anatop module from HW
perspective, so it should be a child node of anatop.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 018e4308

arch/arm/boot/dts/imx6qdl.dtsi

+11 −11
Original line number Diff line number Diff line
@@ -69,17 +69,6 @@ 
		};

	};



	tempmon: tempmon {

		compatible = "fsl,imx6q-tempmon";

		interrupt-parent = <&gpc>;

		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

		fsl,tempmon = <&anatop>;

		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

		nvmem-cell-names = "calib", "temp_grade";

		clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

		#thermal-sensor-cells = <0>;

	};



	ldb: ldb {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -795,6 +784,17 @@ 
					anatop-min-voltage = <725000>;

					anatop-max-voltage = <1450000>;

				};



				tempmon: tempmon {

					compatible = "fsl,imx6q-tempmon";

					interrupt-parent = <&gpc>;

					interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

					fsl,tempmon = <&anatop>;

					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

					nvmem-cell-names = "calib", "temp_grade";

					clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;

					#thermal-sensor-cells = <0>;

				};

			};



			usbphy1: usbphy@20c9000 {

arch/arm/boot/dts/imx6sl.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -93,16 +93,6 @@ 
		};

	};



	tempmon: tempmon {

		compatible = "fsl,imx6q-tempmon";

		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gpc>;

		fsl,tempmon = <&anatop>;

		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

		nvmem-cell-names = "calib", "temp_grade";

		clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&gpc>;
@@ -628,6 +618,16 @@ 
					anatop-min-voltage = <725000>;

					anatop-max-voltage = <1450000>;

				};



				tempmon: tempmon {

					compatible = "fsl,imx6q-tempmon";

					interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;

					interrupt-parent = <&gpc>;

					fsl,tempmon = <&anatop>;

					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

					nvmem-cell-names = "calib", "temp_grade";

					clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;

				};

			};



			usbphy1: usbphy@20c9000 {

arch/arm/boot/dts/imx6sll.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -105,16 +105,6 @@ 
		clock-output-names = "ipp_di1";

	};



	tempmon: temperature-sensor {

		compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";

		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gpc>;

		fsl,tempmon = <&anatop>;

		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

		nvmem-cell-names = "calib", "temp_grade";

		clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;
@@ -531,6 +521,16 @@ 
					anatop-max-voltage = <3400000>;

					anatop-enable-bit = <0>;

				};



				tempmon: temperature-sensor {

					compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";

					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

					interrupt-parent = <&gpc>;

					fsl,tempmon = <&anatop>;

					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

					nvmem-cell-names = "calib", "temp_grade";

					clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;

				};

			};



			usbphy1: usb-phy@20c9000 {

arch/arm/boot/dts/imx6sx.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -134,16 +134,6 @@ 
		clock-output-names = "anaclk2";

	};



	tempmon: tempmon {

		compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";

		interrupt-parent = <&gpc>;

		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

		fsl,tempmon = <&anatop>;

		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

		nvmem-cell-names = "calib", "temp_grade";

		clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&gpc>;
@@ -696,6 +686,16 @@ 
					anatop-min-voltage = <725000>;

					anatop-max-voltage = <1450000>;

				};



				tempmon: tempmon {

					compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";

					interrupt-parent = <&gpc>;

					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

					fsl,tempmon = <&anatop>;

					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

					nvmem-cell-names = "calib", "temp_grade";

					clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;

				};

			};



			usbphy1: usbphy@20c9000 {

arch/arm/boot/dts/imx6ul.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -131,16 +131,6 @@ 
		clock-output-names = "ipp_di1";

	};



	tempmon: tempmon {

		compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";

		interrupt-parent = <&gpc>;

		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

		fsl,tempmon = <&anatop>;

		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

		nvmem-cell-names = "calib", "temp_grade";

		clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;

	};



	pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupt-parent = <&gpc>;
@@ -612,6 +602,16 @@ 
					anatop-min-voltage = <725000>;

					anatop-max-voltage = <1450000>;

				};



				tempmon: tempmon {

					compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";

					interrupt-parent = <&gpc>;

					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

					fsl,tempmon = <&anatop>;

					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;

					nvmem-cell-names = "calib", "temp_grade";

					clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;

				};

			};



			usbphy1: usbphy@20c9000 {

CRA Git | Maintained and supported by SUSTech CRA and CCSE