Commit 9142b673 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-mvpp2-MAC-GoP-configuration' 



Antoine Tenart says:

====================
net: mvpp2: MAC/GoP configuration

This is based on net-next (e2a7c34f).

I removed the GoP interrupt and PHY optional parts in this v2 to ease
the review process as the MAC/GoP initialization seemed to start less
discussions :)

This series now only aims at making the PPv2 driver less depending on
the firmware/bootloader initialization. Some patches cleanup some parts
as well, and add new interface descriptions in the dt.

The current implementation of the PPv2 driver relies on the
firmware/bootloader initialization to configure some parts, as the Group
of Ports (GoP) and the MACs (GMAC and/or XLG MAC --for 10G--).  The
drawback is the kernel must be configured to match exactly what the
bootloader configures which is not convenient and is an issue when using
boards having an Ethernet port and an SFP port wired to the same GoP
port, as no dynamic configuration can be done.

This series adds the GoP and GMAC/XLG MAC initializations so that the
PPV2 does not have to rely on a previous initialization. One part is
still missing from this series, and that would be the 'comphy' which
provides shared serdes PHYs and which must be configured as well for a
full kernel initialization to work. This comphy support will be part of
a following up series. (This series was also tested with this 'comphy'
support, as it's nearly ready).

@Dave: patches 9 and 10 should go through the mvebu tree. Thanks!
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 84e54fe0 7afe461e

Documentation/devicetree/bindings/net/marvell-pp2.txt

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ Optional properties (port): 
                   be the name associated to the interrupts listed. Valid

                   names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3",

		   "rx-shared".

- marvell,system-controller: a phandle to the system controller.



Example for marvell,armada-375-pp2:

drivers/net/ethernet/marvell/mvpp2.c

+360 −72
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <linux/inetdevice.h>

#include <linux/mbus.h>

#include <linux/module.h>

#include <linux/mfd/syscon.h>

#include <linux/interrupt.h>

#include <linux/cpumask.h>

#include <linux/of.h>
@@ -30,6 +31,7 @@ 
#include <linux/clk.h>

#include <linux/hrtimer.h>

#include <linux/ktime.h>

#include <linux/regmap.h>

#include <uapi/linux/ppp_defs.h>

#include <net/ip.h>

#include <net/ipv6.h>
@@ -315,6 +317,7 @@ 
/* Per-port registers */

#define MVPP2_GMAC_CTRL_0_REG			0x0

#define     MVPP2_GMAC_PORT_EN_MASK		BIT(0)

#define     MVPP2_GMAC_PORT_TYPE_MASK		BIT(1)

#define     MVPP2_GMAC_MAX_RX_SIZE_OFFS		2

#define     MVPP2_GMAC_MAX_RX_SIZE_MASK		0x7ffc

#define     MVPP2_GMAC_MIB_CNTR_EN_MASK		BIT(15)
@@ -326,16 +329,21 @@ 
#define     MVPP2_GMAC_SA_LOW_OFFS		7

#define MVPP2_GMAC_CTRL_2_REG			0x8

#define     MVPP2_GMAC_INBAND_AN_MASK		BIT(0)

#define     MVPP2_GMAC_FLOW_CTRL_MASK		GENMASK(2, 1)

#define     MVPP2_GMAC_PCS_ENABLE_MASK		BIT(3)

#define     MVPP2_GMAC_PORT_RGMII_MASK		BIT(4)

#define     MVPP2_GMAC_DISABLE_PADDING		BIT(5)

#define     MVPP2_GMAC_PORT_RESET_MASK		BIT(6)

#define MVPP2_GMAC_AUTONEG_CONFIG		0xc

#define     MVPP2_GMAC_FORCE_LINK_DOWN		BIT(0)

#define     MVPP2_GMAC_FORCE_LINK_PASS		BIT(1)

#define     MVPP2_GMAC_IN_BAND_AUTONEG		BIT(2)

#define     MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS	BIT(3)

#define     MVPP2_GMAC_CONFIG_MII_SPEED	BIT(5)

#define     MVPP2_GMAC_CONFIG_GMII_SPEED	BIT(6)

#define     MVPP2_GMAC_AN_SPEED_EN		BIT(7)

#define     MVPP2_GMAC_FC_ADV_EN		BIT(9)

#define     MVPP2_GMAC_FLOW_CTRL_AUTONEG	BIT(11)

#define     MVPP2_GMAC_CONFIG_FULL_DUPLEX	BIT(12)

#define     MVPP2_GMAC_AN_DUPLEX_EN		BIT(13)

#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG		0x1c
@@ -346,7 +354,7 @@ 
#define MVPP22_GMAC_CTRL_4_REG			0x90

#define     MVPP22_CTRL4_EXT_PIN_GMII_SEL	BIT(0)

#define     MVPP22_CTRL4_DP_CLK_SEL		BIT(5)

#define      MVPP22_CTRL4_SYNC_BYPASS		BIT(6)

#define     MVPP22_CTRL4_SYNC_BYPASS_DIS	BIT(6)

#define     MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE	BIT(7)



/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
@@ -355,13 +363,21 @@ 
#define MVPP22_XLG_CTRL0_REG			0x100

#define     MVPP22_XLG_CTRL0_PORT_EN		BIT(0)

#define     MVPP22_XLG_CTRL0_MAC_RESET_DIS	BIT(1)

#define     MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN	BIT(7)

#define     MVPP22_XLG_CTRL0_MIB_CNT_DIS	BIT(14)



#define MVPP22_XLG_CTRL1_REG			0x104

#define     MVPP22_XLG_CTRL1_FRAMESIZELIMIT	BIT(0)

#define     MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK	0x1fff

#define MVPP22_XLG_CTRL3_REG			0x11c

#define     MVPP22_XLG_CTRL3_MACMODESELECT_MASK	(7 << 13)

#define     MVPP22_XLG_CTRL3_MACMODESELECT_GMAC	(0 << 13)

#define     MVPP22_XLG_CTRL3_MACMODESELECT_10G	(1 << 13)



#define MVPP22_XLG_CTRL4_REG			0x184

#define     MVPP22_XLG_CTRL4_FWD_FC		BIT(5)

#define     MVPP22_XLG_CTRL4_FWD_PFC		BIT(6)

#define     MVPP22_XLG_CTRL4_MACMODSELECT_GMAC	BIT(12)



/* SMI registers. PPv2.2 only, relative to priv->iface_base. */

#define MVPP22_SMI_MISC_CFG_REG			0x1204

#define     MVPP22_SMI_POLLING_EN		BIT(10)
@@ -374,6 +390,38 @@ 
#define MVPP2_QUEUE_NEXT_DESC(q, index) \

	(((index) < (q)->last_desc) ? ((index) + 1) : 0)



/* XPCS registers. PPv2.2 only */

#define MVPP22_MPCS_BASE(port)			(0x7000 + (port) * 0x1000)

#define MVPP22_MPCS_CTRL			0x14

#define     MVPP22_MPCS_CTRL_FWD_ERR_CONN	BIT(10)

#define MVPP22_MPCS_CLK_RESET			0x14c

#define     MAC_CLK_RESET_SD_TX			BIT(0)

#define     MAC_CLK_RESET_SD_RX			BIT(1)

#define     MAC_CLK_RESET_MAC			BIT(2)

#define     MVPP22_MPCS_CLK_RESET_DIV_RATIO(n)	((n) << 4)

#define     MVPP22_MPCS_CLK_RESET_DIV_SET	BIT(11)



/* XPCS registers. PPv2.2 only */

#define MVPP22_XPCS_BASE(port)			(0x7400 + (port) * 0x1000)

#define MVPP22_XPCS_CFG0			0x0

#define     MVPP22_XPCS_CFG0_PCS_MODE(n)	((n) << 3)

#define     MVPP22_XPCS_CFG0_ACTIVE_LANE(n)	((n) << 5)



/* System controller registers. Accessed through a regmap. */

#define GENCONF_SOFT_RESET1				0x1108

#define     GENCONF_SOFT_RESET1_GOP			BIT(6)

#define GENCONF_PORT_CTRL0				0x1110

#define     GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT		BIT(1)

#define     GENCONF_PORT_CTRL0_RX_DATA_SAMPLE		BIT(29)

#define     GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR	BIT(31)

#define GENCONF_PORT_CTRL1				0x1114

#define     GENCONF_PORT_CTRL1_EN(p)			BIT(p)

#define     GENCONF_PORT_CTRL1_RESET(p)			(BIT(p) << 28)

#define GENCONF_CTRL0					0x1120

#define     GENCONF_CTRL0_PORT0_RGMII			BIT(0)

#define     GENCONF_CTRL0_PORT1_RGMII_MII		BIT(1)

#define     GENCONF_CTRL0_PORT1_RGMII			BIT(2)



/* Various constants */



/* Coalescing */
@@ -717,6 +765,11 @@ struct mvpp2 { 
	 */

	void __iomem *swth_base[MVPP2_MAX_THREADS];



	/* On PPv2.2, some port control registers are located into the system

	 * controller space. These registers are accessible through a regmap.

	 */

	struct regmap *sysctrl_base;



	/* Common clocks */

	struct clk *pp_clk;

	struct clk *gop_clk;
@@ -4245,6 +4298,226 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 


/* Port configuration routines */



static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)

{

	struct mvpp2 *priv = port->priv;

	u32 val;



	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);

	val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;

	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);



	regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);

	if (port->gop_id == 2)

		val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;

	else if (port->gop_id == 3)

		val |= GENCONF_CTRL0_PORT1_RGMII_MII;

	regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);

}



static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)

{

	struct mvpp2 *priv = port->priv;

	u32 val;



	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);

	val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |

	       GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;

	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);



	if (port->gop_id > 1) {

		regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);

		if (port->gop_id == 2)

			val &= ~GENCONF_CTRL0_PORT0_RGMII;

		else if (port->gop_id == 3)

			val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;

		regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);

	}

}



static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)

{

	struct mvpp2 *priv = port->priv;

	void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);

	void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);

	u32 val;



	/* XPCS */

	val = readl(xpcs + MVPP22_XPCS_CFG0);

	val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |

		 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));

	val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);

	writel(val, xpcs + MVPP22_XPCS_CFG0);



	/* MPCS */

	val = readl(mpcs + MVPP22_MPCS_CTRL);

	val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;

	writel(val, mpcs + MVPP22_MPCS_CTRL);



	val = readl(mpcs + MVPP22_MPCS_CLK_RESET);

	val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC |

		 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);

	val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);

	writel(val, mpcs + MVPP22_MPCS_CLK_RESET);



	val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;

	val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX;

	writel(val, mpcs + MVPP22_MPCS_CLK_RESET);

}



static int mvpp22_gop_init(struct mvpp2_port *port)

{

	struct mvpp2 *priv = port->priv;

	u32 val;



	if (!priv->sysctrl_base)

		return 0;



	switch (port->phy_interface) {

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

		if (port->gop_id == 0)

			goto invalid_conf;

		mvpp22_gop_init_rgmii(port);

		break;

	case PHY_INTERFACE_MODE_SGMII:

		mvpp22_gop_init_sgmii(port);

		break;

	case PHY_INTERFACE_MODE_10GKR:

		if (port->gop_id != 0)

			goto invalid_conf;

		mvpp22_gop_init_10gkr(port);

		break;

	default:

		goto unsupported_conf;

	}



	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);

	val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |

	       GENCONF_PORT_CTRL1_EN(port->gop_id);

	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);



	regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);

	val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;

	regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);



	regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);

	val |= GENCONF_SOFT_RESET1_GOP;

	regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);



unsupported_conf:

	return 0;



invalid_conf:

	netdev_err(port->dev, "Invalid port configuration\n");

	return -EINVAL;

}



static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)

{

	u32 val;



	if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {

		val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);

		val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |

		       MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;

		val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;

		writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);



		val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);

		val |= MVPP2_GMAC_DISABLE_PADDING;

		val &= ~MVPP2_GMAC_FLOW_CTRL_MASK;

		writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);

	} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||

		   port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||

		   port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||

		   port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {

		val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);

		val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |

		       MVPP22_CTRL4_SYNC_BYPASS_DIS |

		       MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;

		val &= ~MVPP22_CTRL4_DP_CLK_SEL;

		writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);



		val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);

		val &= ~MVPP2_GMAC_DISABLE_PADDING;

		writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);

	}



	/* The port is connected to a copper PHY */

	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);

	val &= ~MVPP2_GMAC_PORT_TYPE_MASK;

	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);



	val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);

	val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |

	       MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |

	       MVPP2_GMAC_AN_DUPLEX_EN;

	if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)

		val |= MVPP2_GMAC_IN_BAND_AUTONEG;

	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);

}



static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)

{

	u32 val;



	/* Force link down */

	val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);

	val &= ~MVPP2_GMAC_FORCE_LINK_PASS;

	val |= MVPP2_GMAC_FORCE_LINK_DOWN;

	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);



	/* Set the GMAC in a reset state */

	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);

	val |= MVPP2_GMAC_PORT_RESET_MASK;

	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);



	/* Configure the PCS and in-band AN */

	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);

	if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {

	        val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;

	} else if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||

		   port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||

		   port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||

		   port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {

		val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;

		val |= MVPP2_GMAC_PORT_RGMII_MASK;

	}

	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);



	mvpp2_port_mii_gmac_configure_mode(port);



	/* Unset the GMAC reset state */

	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);

	val &= ~MVPP2_GMAC_PORT_RESET_MASK;

	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);



	/* Stop forcing link down */

	val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);

	val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;

	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);

}



static void mvpp2_port_mii_xlg_configure(struct mvpp2_port *port)

{

	u32 val;



	if (port->gop_id != 0)

		return;



	val = readl(port->base + MVPP22_XLG_CTRL0_REG);

	val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;

	writel(val, port->base + MVPP22_XLG_CTRL0_REG);



	val = readl(port->base + MVPP22_XLG_CTRL4_REG);

	val &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;

	val |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC;

	writel(val, port->base + MVPP22_XLG_CTRL4_REG);

}



static void mvpp22_port_mii_set(struct mvpp2_port *port)

{

	u32 val;
@@ -4262,38 +4535,21 @@ static void mvpp22_port_mii_set(struct mvpp2_port *port) 


		writel(val, port->base + MVPP22_XLG_CTRL3_REG);

	}



	val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);

	if (port->phy_interface == PHY_INTERFACE_MODE_RGMII)

		val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL;

	else

		val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;

	val &= ~MVPP22_CTRL4_DP_CLK_SEL;

	val |= MVPP22_CTRL4_SYNC_BYPASS;

	val |= MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;

	writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);

}



static void mvpp2_port_mii_set(struct mvpp2_port *port)

{

	u32 val;



	if (port->priv->hw_version == MVPP22)

		mvpp22_port_mii_set(port);



	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);



	switch (port->phy_interface) {

	case PHY_INTERFACE_MODE_SGMII:

		val |= MVPP2_GMAC_INBAND_AN_MASK;

		break;

	case PHY_INTERFACE_MODE_RGMII:

		val |= MVPP2_GMAC_PORT_RGMII_MASK;

	default:

		val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;

	}



	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);

	if (port->phy_interface == PHY_INTERFACE_MODE_RGMII ||

	    port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||

	    port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||

	    port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID ||

	    port->phy_interface == PHY_INTERFACE_MODE_SGMII)

		mvpp2_port_mii_gmac_configure(port);

	else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)

		mvpp2_port_mii_xlg_configure(port);

}



static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
@@ -4400,6 +4656,18 @@ static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 
	writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);

}



/* Change maximum receive size of the port */

static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)

{

	u32 val;



	val =  readl(port->base + MVPP22_XLG_CTRL1_REG);

	val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;

	val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<

	       MVPP22_XLG_CTRL1_FRAMESIZELIMIT;

	writel(val, port->base + MVPP22_XLG_CTRL1_REG);

}



/* Set defaults to the MVPP2 port */

static void mvpp2_defaults_set(struct mvpp2_port *port)

{
@@ -5978,7 +6246,13 @@ static void mvpp2_start_dev(struct mvpp2_port *port) 
	struct net_device *ndev = port->dev;

	int i;



	if (port->gop_id == 0 &&

	    (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||

	     port->phy_interface == PHY_INTERFACE_MODE_10GKR))

		mvpp2_xlg_max_rx_size_set(port);

	else

		mvpp2_gmac_max_rx_size_set(port);



	mvpp2_txp_max_tx_size_set(port);



	for (i = 0; i < port->nqvecs; i++)
@@ -5987,6 +6261,10 @@ static void mvpp2_start_dev(struct mvpp2_port *port) 
	/* Enable interrupts on all CPUs */

	mvpp2_interrupts_enable(port);



	if (port->priv->hw_version == MVPP22)

		mvpp22_gop_init(port);



	mvpp2_port_mii_set(port);

	mvpp2_port_enable(port);

	phy_start(ndev->phydev);

	netif_tx_start_all_queues(port->dev);
@@ -6949,7 +7227,6 @@ static int mvpp2_port_probe(struct platform_device *pdev, 
		goto err_free_stats;

	}



	mvpp2_port_mii_set(port);

	mvpp2_port_periodic_xon_disable(port);



	if (priv->hw_version == MVPP21)
@@ -7232,6 +7509,17 @@ static int mvpp2_probe(struct platform_device *pdev) 
		priv->iface_base = devm_ioremap_resource(&pdev->dev, res);

		if (IS_ERR(priv->iface_base))

			return PTR_ERR(priv->iface_base);



		priv->sysctrl_base =

			syscon_regmap_lookup_by_phandle(pdev->dev.of_node,

							"marvell,system-controller");

		if (IS_ERR(priv->sysctrl_base))

			/* The system controller regmap is optional for dt

			 * compatibility reasons. When not provided, the

			 * configuration of the GoP relies on the

			 * firmware/bootloader.

			 */

			priv->sysctrl_base = NULL;

	}



	for (i = 0; i < MVPP2_MAX_THREADS; i++) {

CRA Git | Maintained and supported by SUSTech CRA and CCSE