Commit 911ad0b6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2019-09-11' of... 

Merge tag 'drm-intel-fixes-2019-09-11' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

Final drm/i915 fixes for v5.3:
- Fox DP MST high color depth regression
- Fix GPU hangs on Vulkan compute workloads

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/877e6e27qm.fsf@intel.com
parents f74c2bb9 2eb0964e

drivers/gpu/drm/i915/display/intel_dp_mst.c

+9 −1
Original line number Diff line number Diff line
@@ -128,7 +128,15 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 
	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);



	limits.min_bpp = intel_dp_min_bpp(pipe_config);

	limits.max_bpp = pipe_config->pipe_bpp;

	/*

	 * FIXME: If all the streams can't fit into the link with

	 * their current pipe_bpp we should reduce pipe_bpp across

	 * the board until things start to fit. Until then we

	 * limit to <= 8bpc since that's what was hardcoded for all

	 * MST streams previously. This hack should be removed once

	 * we have the proper retry logic in place.

	 */

	limits.max_bpp = min(pipe_config->pipe_bpp, 24);



	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);

drivers/gpu/drm/i915/gt/intel_workarounds.c

+0 −5
Original line number Diff line number Diff line
@@ -308,11 +308,6 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 
			  FLOW_CONTROL_ENABLE |

			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);



	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */

	if (!IS_COFFEELAKE(i915))

		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,

				  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);



	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */

	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */

	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,

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