Commit 9105996b authored by Chris Brandt's avatar Chris Brandt Committed by Simon Horman
Browse files

ARM: dts: r7s9210: Add RSPI



Add RSPI support for RZ/A2 SoC.

Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent a188339c
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+45 −0
Original line number Diff line number Diff line
@@ -146,6 +146,51 @@
			status = "disabled";
		};

		spi0: spi@e800c800 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800c800 0x24>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 97>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@e800d000 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800d000 0x24>;
			interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 96>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@e800d800 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800d800 0x24>;
			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 95>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ostm0: timer@e803b000 {
			compatible = "renesas,r7s9210-ostm", "renesas,ostm";
			reg = <0xe803b000 0x30>;