iommu/io-pgtable-arm: Add support to use system cache (90ec7a76) · Commits · 戴 / test

Few Qualcomm platforms such as, sdm845 have an additional outer cache called as System cache, aka. Last level cache (LLC) that allows non-coherent devices to upgrade to using caching. This cache sits right before the DDR, and is tightly coupled with the memory controller. The clients using this cache request their slices from this system cache, make it active, and can then start using it. There is a fundamental assumption that non-coherent devices can't access caches. This change adds an exception where they *can* use some level of cache despite still being non-coherent overall. The coherent devices that use cacheable memory, and CPU make use of this system cache by default. Looking at memory types, we have following - a) Normal uncached :- MAIR 0x44, inner non-cacheable, outer non-cacheable; b) Normal cached :- MAIR 0xff, inner read write-back non-transient, outer read write-back non-transient; attribute setting for coherenet I/O devices. and, for non-coherent i/o devices that can allocate in system cache another type gets added - c) Normal sys-cached :- MAIR 0xf4, inner non-cacheable, outer read write-back non-transient Coherent I/O devices use system cache by marking the memory as normal cached. Non-coherent I/O devices should mark the memory as normal sys-cached in page tables to use system cache. Acked-by:

Robin Murphy <robin.murphy@arm.com> Signed-off-by:

Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by:

Will Deacon <will.deacon@arm.com>

drivers/iommu/io-pgtable-arm.c

+8 −1

Original line number	Diff line number	Diff line
		@@ -167,10 +167,12 @@
		#define ARM_LPAE_MAIR_ATTR_MASK 0xff
		#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
		#define ARM_LPAE_MAIR_ATTR_NC 0x44
		#define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4
		#define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
		#define ARM_LPAE_MAIR_ATTR_IDX_NC 0
		#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
		#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
		#define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3

		#define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
		#define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
		@@ -470,6 +472,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
		else if (prot & IOMMU_CACHE)
		pte \|= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
		<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
		else if (prot & IOMMU_QCOM_SYS_CACHE)
		pte \|= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
		<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
		}

		if (prot & IOMMU_NOEXEC)
		@@ -857,7 +862,9 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg cfg, void cookie)
		(ARM_LPAE_MAIR_ATTR_WBRWA
		<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) \|
		(ARM_LPAE_MAIR_ATTR_DEVICE
		<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
		<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)) \|
		(ARM_LPAE_MAIR_ATTR_INC_OWBRWA
		<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE));

		cfg->arm_lpae_s1_cfg.mair[0] = reg;
		cfg->arm_lpae_s1_cfg.mair[1] = 0;

include/linux/iommu.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -41,6 +41,12 @@
		* if the IOMMU page table format is equivalent.
		*/
		#define IOMMU_PRIV (1 << 5)
		/*
		* Non-coherent masters on few Qualcomm SoCs can use this page protection flag
		* to set correct cacheability attributes to use an outer level of cache -
		* last level cache, aka system cache.
		*/
		#define IOMMU_QCOM_SYS_CACHE (1 << 6)

		struct iommu_ops;
		struct iommu_group;

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