Commit 90db71e4 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Bjorn Andersson
Browse files

arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc 



Add skeletal sc7180 SoC dtsi and idp board dts files.

Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Co-developed-by: default avatarTaniya Das <tdas@codeaurora.org>
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/20191108092824.9773-3-rnayak@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent f1cbee2d

arch/arm64/boot/dts/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb 
dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-hp-envy-x2.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-lenovo-miix-630.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-mtp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r1.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r2.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r3.dtb

arch/arm64/boot/dts/qcom/sc7180-idp.dts

0 → 100644
+47 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: BSD-3-Clause

/*

 * SC7180 IDP board device tree source

 *

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



/dts-v1/;



#include "sc7180.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. SC7180 IDP";

	compatible = "qcom,sc7180-idp";



	aliases {

		serial0 = &uart8;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};

};



&qupv3_id_1 {

	status = "okay";

};



&uart8 {

	status = "okay";

};



/* PINCTRL - additions to nodes defined in sc7180.dtsi */



&qup_uart8_default {

	pinconf-tx {

		pins = "gpio44";

		drive-strength = <2>;

		bias-disable;

	};



	pinconf-rx {

		pins = "gpio45";

		drive-strength = <2>;

		bias-pull-up;

	};

};

arch/arm64/boot/dts/qcom/sc7180.dtsi

0 → 100644
+298 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: BSD-3-Clause

/*

 * SC7180 SoC device tree source

 *

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#include <dt-bindings/clock/qcom,gcc-sc7180.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	interrupt-parent = <&intc>;



	#address-cells = <2>;

	#size-cells = <2>;



	chosen { };



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			clock-frequency = <38400000>;

			#clock-cells = <0>;

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32764>;

			#clock-cells = <0>;

		};

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

				L3_0: l3-cache {

					compatible = "cache";

				};

			};

		};



		CPU1: cpu@100 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU2: cpu@200 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU3: cpu@300 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU4: cpu@400 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_400>;

			L2_400: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU5: cpu@500 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_500>;

			L2_500: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU6: cpu@600 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_600>;

			L2_600: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU7: cpu@700 {

			device_type = "cpu";

			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_700>;

			L2_700: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};

	};



	memory@80000000 {

		device_type = "memory";

		/* We expect the bootloader to fill in the size */

		reg = <0 0x80000000 0 0>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	soc: soc {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges = <0 0 0 0 0x10 0>;

		dma-ranges = <0 0 0 0 0x10 0>;

		compatible = "simple-bus";



		gcc: clock-controller@100000 {

			compatible = "qcom,gcc-sc7180";

			reg = <0 0x00100000 0 0x1f0000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		qupv3_id_1: geniqup@ac0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0 0x00ac0000 0 0x6000>;

			clock-names = "m-ahb", "s-ahb";

			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,

				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			status = "disabled";



			uart8: serial@a88000 {

				compatible = "qcom,geni-debug-uart";

				reg = <0 0x00a88000 0 0x4000>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;

				pinctrl-names = "default";

				pinctrl-0 = <&qup_uart8_default>;

				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};

		};



		tlmm: pinctrl@3500000 {

			compatible = "qcom,sc7180-pinctrl";

			reg = <0 0x03500000 0 0x300000>,

			      <0 0x03900000 0 0x300000>,

			      <0 0x03d00000 0 0x300000>;

			reg-names = "west", "north", "south";

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&tlmm 0 0 120>;



			qup_uart8_default: qup-uart8-default {

				pinmux {

					pins = "gpio44", "gpio45";

					function = "qup12";

				};

			};

		};



		intc: interrupt-controller@17a00000 {

			compatible = "arm,gic-v3";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0 0x17a00000 0 0x10000>,     /* GICD */

			      <0 0x17a60000 0 0x100000>;    /* GICR * 8 */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



			gic-its@17a40000 {

				compatible = "arm,gic-v3-its";

				msi-controller;

				#msi-cells = <1>;

				reg = <0 0x17a40000 0 0x20000>;

				status = "disabled";

			};

		};



		timer@17c20000{

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0 0x17c20000 0 0x1000>;



			frame@17c21000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0 0x17c21000 0 0x1000>,

				      <0 0x17c22000 0 0x1000>;

			};



			frame@17c23000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0 0x17c23000 0 0x1000>;

				status = "disabled";

			};



			frame@17c25000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0 0x17c25000 0 0x1000>;

				status = "disabled";

			};



			frame@17c27000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0 0x17c27000 0 0x1000>;

				status = "disabled";

			};



			frame@17c29000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0 0x17c29000 0 0x1000>;

				status = "disabled";

			};



			frame@17c2b000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0 0x17c2b000 0 0x1000>;

				status = "disabled";

			};



			frame@17c2d000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0 0x17c2d000 0 0x1000>;

				status = "disabled";

			};

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;

	};

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE