Commit 90d53a91 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ralf Baechle
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MIPS: math-emu: Add IEEE Std 754-2008 NaN encoding emulation 



Implement IEEE Std 754-2008 NaN encoding wired to the state of the
FCSR.NAN2008 bit.  Make the interpretation of the quiet bit in NaN data
as follows:

* in the legacy mode originally defined by the MIPS architecture the
  value of 1 denotes an sNaN whereas the value of 0 denotes a qNaN,

* in the 2008 mode introduced with revision 5 of the MIPS architecture
  the value of 0 denotes an sNaN whereas the value of 1 denotes a qNaN,
  following the definition of the preferred NaN encoding introduced with
  IEEE Std 754-2008.

In the 2008 mode, following the requirement of the said standard, quiet
an sNaN where needed by setting the quiet bit to 1 and leaving all the
NaN payload bits unchanged.

Update format conversion operations according to the rules set by IEEE
Std 754-2008 and the MIPS architecture.  Specifically:

* propagate NaN payload bits through conversions between floating-point
  formats such that as much information as possible is preserved and
  specifically a conversion from a narrower format to a wider format and
  then back to the original format does not change a qNaN payload in any
  way,

* conversions from a floating-point to an integer format where the
  source is a NaN, infinity or a value that would convert to an integer
  outside the range of the result format produce, under the default
  exception handling, the respective values defined by the MIPS
  architecture.

In full FPU emulation set the FIR.HAS2008 bit to 1, however do not make
any further FCSR bits writable.

Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11477/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 198f7058

arch/mips/kernel/cpu-probe.c

+2 −0
Original line number Diff line number Diff line
@@ -113,6 +113,8 @@ static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 
	if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |

			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))

		value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;

	if (c->options & MIPS_CPU_NAN_2008)

		value |= MIPS_FPIR_HAS2008;

	c->fpu_id = value;

}

arch/mips/math-emu/dp_tint.c

+6 −3
Original line number Diff line number Diff line
@@ -38,10 +38,13 @@ int ieee754dp_tint(union ieee754dp x) 
	switch (xc) {

	case IEEE754_CLASS_SNAN:

	case IEEE754_CLASS_QNAN:

	case IEEE754_CLASS_INF:

		ieee754_setcx(IEEE754_INVALID_OPERATION);

		return ieee754si_indef();



	case IEEE754_CLASS_INF:

		ieee754_setcx(IEEE754_INVALID_OPERATION);

		return ieee754si_overflow(xs);



	case IEEE754_CLASS_ZERO:

		return 0;
@@ -53,7 +56,7 @@ int ieee754dp_tint(union ieee754dp x) 
		/* Set invalid. We will only use overflow for floating

		   point overflow */

		ieee754_setcx(IEEE754_INVALID_OPERATION);

		return ieee754si_indef();

		return ieee754si_overflow(xs);

	}

	/* oh gawd */

	if (xe > DP_FBITS) {
@@ -93,7 +96,7 @@ int ieee754dp_tint(union ieee754dp x) 
		if ((xm >> 31) != 0 && (xs == 0 || xm != 0x80000000)) {

			/* This can happen after rounding */

			ieee754_setcx(IEEE754_INVALID_OPERATION);

			return ieee754si_indef();

			return ieee754si_overflow(xs);

		}

		if (round || sticky)

			ieee754_setcx(IEEE754_INEXACT);

arch/mips/math-emu/dp_tlong.c

+6 −3
Original line number Diff line number Diff line
@@ -38,10 +38,13 @@ s64 ieee754dp_tlong(union ieee754dp x) 
	switch (xc) {

	case IEEE754_CLASS_SNAN:

	case IEEE754_CLASS_QNAN:

	case IEEE754_CLASS_INF:

		ieee754_setcx(IEEE754_INVALID_OPERATION);

		return ieee754di_indef();



	case IEEE754_CLASS_INF:

		ieee754_setcx(IEEE754_INVALID_OPERATION);

		return ieee754di_overflow(xs);



	case IEEE754_CLASS_ZERO:

		return 0;
@@ -56,7 +59,7 @@ s64 ieee754dp_tlong(union ieee754dp x) 
		/* Set invalid. We will only use overflow for floating

		   point overflow */

		ieee754_setcx(IEEE754_INVALID_OPERATION);

		return ieee754di_indef();

		return ieee754di_overflow(xs);

	}

	/* oh gawd */

	if (xe > DP_FBITS) {
@@ -97,7 +100,7 @@ s64 ieee754dp_tlong(union ieee754dp x) 
		if ((xm >> 63) != 0) {

			/* This can happen after rounding */

			ieee754_setcx(IEEE754_INVALID_OPERATION);

			return ieee754di_indef();

			return ieee754di_overflow(xs);

		}

		if (round || sticky)

			ieee754_setcx(IEEE754_INEXACT);

arch/mips/math-emu/ieee754.c

+4 −2
Original line number Diff line number Diff line
@@ -59,7 +59,8 @@ const union ieee754dp __ieee754dp_spcvals[] = { 
	DPCNST(1, 3,           0x4000000000000ULL),	/* - 10.0   */

	DPCNST(0, DP_EMAX + 1, 0x0000000000000ULL),	/* + infinity */

	DPCNST(1, DP_EMAX + 1, 0x0000000000000ULL),	/* - infinity */

	DPCNST(0, DP_EMAX + 1, 0x7FFFFFFFFFFFFULL),	/* + indef quiet Nan */

	DPCNST(0, DP_EMAX + 1, 0x7FFFFFFFFFFFFULL),	/* + ind legacy qNaN */

	DPCNST(0, DP_EMAX + 1, 0x8000000000000ULL),	/* + indef 2008 qNaN */

	DPCNST(0, DP_EMAX,     0xFFFFFFFFFFFFFULL),	/* + max */

	DPCNST(1, DP_EMAX,     0xFFFFFFFFFFFFFULL),	/* - max */

	DPCNST(0, DP_EMIN,     0x0000000000000ULL),	/* + min normal */
@@ -82,7 +83,8 @@ const union ieee754sp __ieee754sp_spcvals[] = { 
	SPCNST(1, 3,	       0x200000),	/* - 10.0   */

	SPCNST(0, SP_EMAX + 1, 0x000000),	/* + infinity */

	SPCNST(1, SP_EMAX + 1, 0x000000),	/* - infinity */

	SPCNST(0, SP_EMAX + 1, 0x3FFFFF),	/* + indef quiet Nan  */

	SPCNST(0, SP_EMAX + 1, 0x3FFFFF),	/* + indef legacy quiet NaN */

	SPCNST(0, SP_EMAX + 1, 0x400000),	/* + indef 2008 quiet NaN */

	SPCNST(0, SP_EMAX,     0x7FFFFF),	/* + max normal */

	SPCNST(1, SP_EMAX,     0x7FFFFF),	/* - max normal */

	SPCNST(0, SP_EMIN,     0x000000),	/* + min normal */

arch/mips/math-emu/ieee754.h

+29 −13
Original line number Diff line number Diff line
@@ -221,15 +221,16 @@ union ieee754dp ieee754dp_dump(char *s, union ieee754dp x); 
#define IEEE754_SPCVAL_NTEN		5	/* -10.0 */

#define IEEE754_SPCVAL_PINFINITY	6	/* +inf */

#define IEEE754_SPCVAL_NINFINITY	7	/* -inf */

#define IEEE754_SPCVAL_INDEF		8	/* quiet NaN */

#define IEEE754_SPCVAL_PMAX		9	/* +max norm */

#define IEEE754_SPCVAL_NMAX		10	/* -max norm */

#define IEEE754_SPCVAL_PMIN		11	/* +min norm */

#define IEEE754_SPCVAL_NMIN		12	/* -min norm */

#define IEEE754_SPCVAL_PMIND		13	/* +min denorm */

#define IEEE754_SPCVAL_NMIND		14	/* -min denorm */

#define IEEE754_SPCVAL_P1E31		15	/* + 1.0e31 */

#define IEEE754_SPCVAL_P1E63		16	/* + 1.0e63 */

#define IEEE754_SPCVAL_INDEF_LEG	8	/* legacy quiet NaN */

#define IEEE754_SPCVAL_INDEF_2008	9	/* IEEE 754-2008 quiet NaN */

#define IEEE754_SPCVAL_PMAX		10	/* +max norm */

#define IEEE754_SPCVAL_NMAX		11	/* -max norm */

#define IEEE754_SPCVAL_PMIN		12	/* +min norm */

#define IEEE754_SPCVAL_NMIN		13	/* -min norm */

#define IEEE754_SPCVAL_PMIND		14	/* +min denorm */

#define IEEE754_SPCVAL_NMIND		15	/* -min denorm */

#define IEEE754_SPCVAL_P1E31		16	/* + 1.0e31 */

#define IEEE754_SPCVAL_P1E63		17	/* + 1.0e63 */



extern const union ieee754dp __ieee754dp_spcvals[];

extern const union ieee754sp __ieee754sp_spcvals[];
@@ -243,7 +244,8 @@ extern const union ieee754sp __ieee754sp_spcvals[]; 
#define ieee754dp_zero(sn)	(ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])

#define ieee754dp_one(sn)	(ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)])

#define ieee754dp_ten(sn)	(ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])

#define ieee754dp_indef()	(ieee754dp_spcvals[IEEE754_SPCVAL_INDEF])

#define ieee754dp_indef()	(ieee754dp_spcvals[IEEE754_SPCVAL_INDEF_LEG + \

						   ieee754_csr.nan2008])

#define ieee754dp_max(sn)	(ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])

#define ieee754dp_min(sn)	(ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])

#define ieee754dp_mind(sn)	(ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
@@ -254,7 +256,8 @@ extern const union ieee754sp __ieee754sp_spcvals[]; 
#define ieee754sp_zero(sn)	(ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)])

#define ieee754sp_one(sn)	(ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)])

#define ieee754sp_ten(sn)	(ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)])

#define ieee754sp_indef()	(ieee754sp_spcvals[IEEE754_SPCVAL_INDEF])

#define ieee754sp_indef()	(ieee754sp_spcvals[IEEE754_SPCVAL_INDEF_LEG + \

						   ieee754_csr.nan2008])

#define ieee754sp_max(sn)	(ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)])

#define ieee754sp_min(sn)	(ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)])

#define ieee754sp_mind(sn)	(ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)])
@@ -266,12 +269,25 @@ extern const union ieee754sp __ieee754sp_spcvals[]; 
 */

static inline int ieee754si_indef(void)

{

	return INT_MAX;

	return ieee754_csr.nan2008 ? 0 : INT_MAX;

}



static inline s64 ieee754di_indef(void)

{

	return S64_MAX;

	return ieee754_csr.nan2008 ? 0 : S64_MAX;

}



/*

 * Overflow integer value

 */

static inline int ieee754si_overflow(int xs)

{

	return ieee754_csr.nan2008 && xs ? INT_MIN : INT_MAX;

}



static inline s64 ieee754di_overflow(int xs)

{

	return ieee754_csr.nan2008 && xs ? S64_MIN : S64_MAX;

}



/* result types for xctx.rt */

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