Commit 90c559b1 authored by Lijun Ou's avatar Lijun Ou Committed by Doug Ledford
Browse files

RDMA/hns: Remove the some magic number



Here uses the meaningful macro instead of the magic number
for readability.

Signed-off-by: default avatarLijun Ou <oulijun@huawei.com>
Signed-off-by: default avatarLang Chen <chenglang@huawei.com>
Link: https://lore.kernel.org/r/1566393276-42555-5-git-send-email-oulijun@huawei.com


Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent 82e620d9
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+5 −0
Original line number Diff line number Diff line
@@ -127,6 +127,11 @@
#define HNS_ROCE_IDX_QUE_ENTRY_SZ		4
#define SRQ_DB_REG				0x230

/* The chip implementation of the consumer index is calculated
 * according to twice the actual EQ depth
 */
#define EQ_DEPTH_COEFF				2

enum {
	HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0,
	HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1,
+2 −1
Original line number Diff line number Diff line
@@ -4018,7 +4018,8 @@ static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
		++eq->cons_index;
		ceqes_found = 1;

		if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
		if (eq->cons_index >
		    EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1) {
			dev_warn(&eq->hr_dev->pdev->dev,
				"cons_index overflow, set back to 0.\n");
			eq->cons_index = 0;
+2 −2
Original line number Diff line number Diff line
@@ -5084,7 +5084,7 @@ static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
		++eq->cons_index;
		ceqe_found = 1;

		if (eq->cons_index > (2 * eq->entries - 1)) {
		if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1)) {
			dev_warn(dev, "cons_index overflow, set back to 0.\n");
			eq->cons_index = 0;
		}
@@ -6501,7 +6501,7 @@ static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)

	handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
	dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
	msleep(100);
	msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
	__hns_roce_hw_v2_uninit_instance(handle, false);

	return 0;
+2 −1
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@
#define HNS_ROCE_V2_RSV_QPS			8

#define HNS_ROCE_V2_HW_RST_TIMEOUT		1000
#define HNS_ROCE_V2_HW_RST_UNINT_DELAY		100

#define HNS_ROCE_CONTEXT_HOP_NUM		1
#define HNS_ROCE_SCCC_HOP_NUM			1