soc: mediatek: Refactor polling timeout and documentation (90a94314) · Commits · 戴 / test

drivers/soc/mediatek/mtk-scpsys.c

+12 −1

Original line number	Diff line number	Diff line
		@@ -21,7 +21,7 @@
		#include <dt-bindings/power/mt8173-power.h>

		#define MTK_POLL_DELAY_US 10
		#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
		#define MTK_POLL_TIMEOUT USEC_PER_SEC

		#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
		#define MTK_SCPD_FWAIT_SRAM BIT(1)
		@@ -108,6 +108,17 @@ static const char * const clk_names[] = {

		#define MAX_CLKS 3

		/**
		* struct scp_domain_data - scp domain data for power on/off flow
		* @name: The domain name.
		* @sta_mask: The mask for power on/off status bit.
		* @ctl_offs: The offset for main power control register.
		* @sram_pdn_bits: The mask for sram power control bits.
		* @sram_pdn_ack_bits: The mask for sram power control acked bits.
		* @bus_prot_mask: The mask for single step bus protection.
		* @clk_id: The basic clocks required by this power domain.
		* @caps: The flag for active wake-up action.
		*/
		struct scp_domain_data {
		const char *name;
		u32 sta_mask;