Commit 909d6c6c authored by George G. Davis's avatar George G. Davis Committed by Russell King
Browse files

[ARM] 4453/1: Fully Decode ARM instruction set state in show_regs() tombstone 



The ARM show_regs() tombstone only partially decodes which ARM ISA was
executing at the time a fault occurred displaying either "(T)" for the
Thumb case or nothing at all for other cases.  This patch therefore
explicitly identifies which state the processor is in at the time of
a fault: ARM, Thumb, Jazelle or JazelleEE.

Signed-off-by: default avatarGeorge G. Davis <gdavis@mvista.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 9d20fdd5

arch/arm/kernel/process.c

+6 −2
Original line number Diff line number Diff line
@@ -44,6 +44,10 @@ static const char *processor_modes[] = { 
  "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"

};



static const char *isa_modes[] = {

  "ARM" , "Thumb" , "Jazelle", "ThumbEE"

};



extern void setup_mm_for_reboot(char mode);



static volatile int hlt_counter;
@@ -230,11 +234,11 @@ void __show_regs(struct pt_regs *regs) 
	buf[3] = flags & PSR_V_BIT ? 'V' : 'v';

	buf[4] = '\0';



	printk("Flags: %s  IRQs o%s  FIQs o%s  Mode %s%s  Segment %s\n",

	printk("Flags: %s  IRQs o%s  FIQs o%s  Mode %s  ISA %s  Segment %s\n",

		buf, interrupts_enabled(regs) ? "n" : "ff",

		fast_interrupts_enabled(regs) ? "n" : "ff",

		processor_modes[processor_mode(regs)],

		thumb_mode(regs) ? " (T)" : "",

		isa_modes[isa_mode(regs)],

		get_fs() == get_ds() ? "kernel" : "user");

#ifdef CONFIG_CPU_CP15

	{

include/asm-arm/ptrace.h

+4 −0
Original line number Diff line number Diff line
@@ -103,6 +103,10 @@ struct pt_regs { 
#define thumb_mode(regs) (0)

#endif



#define isa_mode(regs) \

	((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \

	 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))



#define processor_mode(regs) \

	((regs)->ARM_cpsr & MODE_MASK)

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