Commit 9097f5e3 authored by Harunobu Kurokawa's avatar Harunobu Kurokawa Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a7796: Add PCIe clocks 



This patch adds PCIEC{0,1} clocks for R8A7796 SoC.

Signed-off-by: default avatarHarunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a0b381fa

drivers/clk/renesas/r8a7796-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -136,6 +136,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("sdif2",		 312,	R8A7796_CLK_SD2),

	DEF_MOD("sdif1",		 313,	R8A7796_CLK_SD1),

	DEF_MOD("sdif0",		 314,	R8A7796_CLK_SD0),

	DEF_MOD("pcie1",		 318,	R8A7796_CLK_S3D1),

	DEF_MOD("pcie0",		 319,	R8A7796_CLK_S3D1),

	DEF_MOD("usb-dmac0",		 330,	R8A7796_CLK_S3D1),

	DEF_MOD("usb-dmac1",		 331,	R8A7796_CLK_S3D1),

	DEF_MOD("rwdt",			 402,	R8A7796_CLK_R),

CRA Git | Maintained and supported by SUSTech CRA and CCSE