Commit 905e75c4 authored by Jia Hongtao's avatar Jia Hongtao Committed by Kumar Gala
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powerpc/fsl-pci: Unify pci/pcie initialization code



We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function which is architectural better. Also It's convenient for
adding PM support for PCI controller in later patch.

Now we registered pci controllers as platform devices. So we combine two
initialization code as one platform driver.

Signed-off-by: default avatarJia Hongtao <B38951@freescale.com>
Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarChunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 9e67886b
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+10 −0
Original line number Original line Diff line number Diff line
@@ -27,6 +27,16 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
	{ .compatible = "fsl,mpc8548-guts", },
	{ .compatible = "fsl,mpc8548-guts", },
	/* Probably unnecessary? */
	/* Probably unnecessary? */
	{ .compatible = "gpio-leds", },
	{ .compatible = "gpio-leds", },
	/* For all PCI controllers */
	{ .compatible = "fsl,mpc8540-pci", },
	{ .compatible = "fsl,mpc8548-pcie", },
	{ .compatible = "fsl,p1022-pcie", },
	{ .compatible = "fsl,p1010-pcie", },
	{ .compatible = "fsl,p1023-pcie", },
	{ .compatible = "fsl,p4080-pcie", },
	{ .compatible = "fsl,qoriq-pcie-v2.4", },
	{ .compatible = "fsl,qoriq-pcie-v2.3", },
	{ .compatible = "fsl,qoriq-pcie-v2.2", },
	{},
	{},
};
};


+5 −29
Original line number Original line Diff line number Diff line
@@ -16,7 +16,6 @@
#include <linux/kdev_t.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>


#include <asm/time.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/machdep.h>
@@ -52,39 +51,16 @@ void __init corenet_ds_pic_init(void)
 */
 */
void __init corenet_ds_setup_arch(void)
void __init corenet_ds_setup_arch(void)
{
{
#ifdef CONFIG_PCI
	struct device_node *np;
	struct pci_controller *hose;
#endif
	dma_addr_t max = 0xffffffff;

	mpc85xx_smp_init();
	mpc85xx_smp_init();


#ifdef CONFIG_PCI
#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
		    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2") ||
		    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.3") ||
		    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.4")) {
			fsl_add_bridge(np, 0);
			hose = pci_find_hose_for_OF_device(np);
			max = min(max, hose->dma_window_base_cur +
					hose->dma_window_size);
		}
	}

#ifdef CONFIG_PPC64
	pci_devs_phb_init();
	pci_devs_phb_init();
#endif
#endif
#endif


#ifdef CONFIG_SWIOTLB
	fsl_pci_assign_primary();
	if ((memblock_end_of_DRAM() - 1) > max) {

		ppc_swiotlb_enable = 1;
	swiotlb_detect_4g();
		set_pci_dma_ops(&swiotlb_dma_ops);

		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	}
#endif
	pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
	pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
}
}


+20 −42
Original line number Original line Diff line number Diff line
@@ -22,7 +22,6 @@
#include <linux/seq_file.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>


#include <asm/time.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/machdep.h>
@@ -84,53 +83,39 @@ void __init ge_imp3a_pic_init(void)
	of_node_put(cascade_node);
	of_node_put(cascade_node);
}
}


#ifdef CONFIG_PCI
static void ge_imp3a_pci_assign_primary(void)
static int primary_phb_addr;
#endif	/* CONFIG_PCI */

/*
 * Setup the architecture
 */
static void __init ge_imp3a_setup_arch(void)
{
{
	struct device_node *regs;
#ifdef CONFIG_PCI
#ifdef CONFIG_PCI
	struct device_node *np;
	struct device_node *np;
	struct pci_controller *hose;
	struct resource rsrc;
#endif
	dma_addr_t max = 0xffffffff;

	if (ppc_md.progress)
		ppc_md.progress("ge_imp3a_setup_arch()", 0);


#ifdef CONFIG_PCI
	for_each_node_by_type(np, "pci") {
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
		    of_device_is_compatible(np, "fsl,p2020-pcie")) {
		    of_device_is_compatible(np, "fsl,p2020-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == primary_phb_addr)
			if ((rsrc.start & 0xfffff) == 0x9000)
				fsl_add_bridge(np, 1);
				fsl_pci_primary = np;
			else
				fsl_add_bridge(np, 0);

			hose = pci_find_hose_for_OF_device(np);
			max = min(max, hose->dma_window_base_cur +
					hose->dma_window_size);
		}
		}
	}
	}
#endif
#endif
}

/*
 * Setup the architecture
 */
static void __init ge_imp3a_setup_arch(void)
{
	struct device_node *regs;

	if (ppc_md.progress)
		ppc_md.progress("ge_imp3a_setup_arch()", 0);


	mpc85xx_smp_init();
	mpc85xx_smp_init();


#ifdef CONFIG_SWIOTLB
	ge_imp3a_pci_assign_primary();
	if ((memblock_end_of_DRAM() - 1) > max) {

		ppc_swiotlb_enable = 1;
	swiotlb_detect_4g();
		set_pci_dma_ops(&swiotlb_dma_ops);
		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	}
#endif


	/* Remap basic board registers */
	/* Remap basic board registers */
	regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
	regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
@@ -215,17 +200,10 @@ static int __init ge_imp3a_probe(void)
{
{
	unsigned long root = of_get_flat_dt_root();
	unsigned long root = of_get_flat_dt_root();


	if (of_flat_dt_is_compatible(root, "ge,IMP3A")) {
	return of_flat_dt_is_compatible(root, "ge,IMP3A");
#ifdef CONFIG_PCI
		primary_phb_addr = 0x9000;
#endif
		return 1;
	}

	return 0;
}
}


machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices);
machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);


machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);


+3 −33
Original line number Original line Diff line number Diff line
@@ -17,7 +17,6 @@
#include <linux/seq_file.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <linux/of_platform.h>
#include <linux/memblock.h>


#include <asm/time.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/machdep.h>
@@ -46,46 +45,17 @@ void __init mpc8536_ds_pic_init(void)
 */
 */
static void __init mpc8536_ds_setup_arch(void)
static void __init mpc8536_ds_setup_arch(void)
{
{
#ifdef CONFIG_PCI
	struct device_node *np;
	struct pci_controller *hose;
#endif
	dma_addr_t max = 0xffffffff;

	if (ppc_md.progress)
	if (ppc_md.progress)
		ppc_md.progress("mpc8536_ds_setup_arch()", 0);
		ppc_md.progress("mpc8536_ds_setup_arch()", 0);


#ifdef CONFIG_PCI
	fsl_pci_assign_primary();
	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
			struct resource rsrc;
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == 0x8000)
				fsl_add_bridge(np, 1);
			else
				fsl_add_bridge(np, 0);


			hose = pci_find_hose_for_OF_device(np);
	swiotlb_detect_4g();
			max = min(max, hose->dma_window_base_cur +
					hose->dma_window_size);
		}
	}

#endif

#ifdef CONFIG_SWIOTLB
	if ((memblock_end_of_DRAM() - 1) > max) {
		ppc_swiotlb_enable = 1;
		set_pci_dma_ops(&swiotlb_dma_ops);
		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
	}
#endif


	printk("MPC8536 DS board from Freescale Semiconductor\n");
	printk("MPC8536 DS board from Freescale Semiconductor\n");
}
}


machine_device_initcall(mpc8536_ds, mpc85xx_common_publish_devices);
machine_arch_initcall(mpc8536_ds, mpc85xx_common_publish_devices);


machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier);
machine_arch_initcall(mpc8536_ds, swiotlb_setup_bus_notifier);


+3 −8
Original line number Original line Diff line number Diff line
@@ -137,10 +137,6 @@ static void __init init_ioports(void)


static void __init mpc85xx_ads_setup_arch(void)
static void __init mpc85xx_ads_setup_arch(void)
{
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
		ppc_md.progress("mpc85xx_ads_setup_arch()", 0);


@@ -150,11 +146,10 @@ static void __init mpc85xx_ads_setup_arch(void)
#endif
#endif


#ifdef CONFIG_PCI
#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
		fsl_add_bridge(np, 1);

	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
#endif

	fsl_pci_assign_primary();
}
}


static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
@@ -173,7 +168,7 @@ static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
}
}


machine_device_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);


/*
/*
 * Called very early, device-tree isn't unflattened
 * Called very early, device-tree isn't unflattened
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