Unverified Commit 905434e0 authored by Ondrej Jirman's avatar Ondrej Jirman Committed by Maxime Ripard
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arm64: dts: allwinner: h6: Add CPU Operating Performance Points table



Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: default avatarOndrej Jirman <megous@megous.com>
Signed-off-by: default avatarClément Péron <peron.clem@gmail.com>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 9f8a93b7
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+117 −0
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>

/ {
	cpu_opp_table: cpu-opp-table {
		compatible = "allwinner,sun50i-h6-operating-points";
		nvmem-cells = <&cpu_speed_grade>;
		opp-shared;

		opp@480000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <480000000>;

			opp-microvolt-speed0 = <880000>;
			opp-microvolt-speed1 = <820000>;
			opp-microvolt-speed2 = <820000>;
		};

		opp@720000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <720000000>;

			opp-microvolt-speed0 = <880000>;
			opp-microvolt-speed1 = <820000>;
			opp-microvolt-speed2 = <820000>;
		};

		opp@816000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <816000000>;

			opp-microvolt-speed0 = <880000>;
			opp-microvolt-speed1 = <820000>;
			opp-microvolt-speed2 = <820000>;
		};

		opp@888000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <888000000>;

			opp-microvolt-speed0 = <880000>;
			opp-microvolt-speed1 = <820000>;
			opp-microvolt-speed2 = <820000>;
		};

		opp@1080000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <1080000000>;

			opp-microvolt-speed0 = <940000>;
			opp-microvolt-speed1 = <880000>;
			opp-microvolt-speed2 = <880000>;
		};

		opp@1320000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <1320000000>;

			opp-microvolt-speed0 = <1000000>;
			opp-microvolt-speed1 = <940000>;
			opp-microvolt-speed2 = <940000>;
		};

		opp@1488000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <1488000000>;

			opp-microvolt-speed0 = <1060000>;
			opp-microvolt-speed1 = <1000000>;
			opp-microvolt-speed2 = <1000000>;
		};

		opp@1608000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <1608000000>;

			opp-microvolt-speed0 = <1090000>;
			opp-microvolt-speed1 = <1030000>;
			opp-microvolt-speed2 = <1030000>;
		};

		opp@1704000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <1704000000>;

			opp-microvolt-speed0 = <1120000>;
			opp-microvolt-speed1 = <1060000>;
			opp-microvolt-speed2 = <1060000>;
		};

		opp@1800000000 {
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt-speed0 = <1160000>;
			opp-microvolt-speed1 = <1100000>;
			opp-microvolt-speed2 = <1100000>;
		};
	};
};

&cpu0 {
	operating-points-v2 = <&cpu_opp_table>;
};

&cpu1 {
	operating-points-v2 = <&cpu_opp_table>;
};

&cpu2 {
	operating-points-v2 = <&cpu_opp_table>;
};

&cpu3 {
	operating-points-v2 = <&cpu_opp_table>;
};
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@@ -262,6 +262,10 @@
			ths_calibration: thermal-sensor-calibration@14 {
				reg = <0x14 0x8>;
			};

			cpu_speed_grade: cpu-speed-grade@1c {
				reg = <0x1c 0x4>;
			};
		};

		watchdog: watchdog@30090a0 {