Commit 903bfeac authored Jan 01, 2009 by Andy Walls Committed by Mauro Carvalho Chehab Mar 30, 2009

V4L/DVB (10274): cx18: Fix a PLL divisor update for the I2S master clock



A redundant PLL divisior update for the I2S master clock after AV core
firmware load was missed in earlier PLL parameter changes.  This one really
doesn't matter because it's redundant and gets overwritten, but the driver
should be self consistent in the values used.

Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

parent f97d2074

drivers/media/video/cx18/cx18-av-firmware.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -115,9 +115,9 @@ int cx18_av_loadfw(struct cx18 *cx)
		are generated) */
		cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);

		/* set alt I2s master clock to /16 and enable alt divider i2s
		/* set alt I2s master clock to /0x16 and enable alt divider i2s
		passthrough */
		cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5000B687);
		cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);

		cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
		0x3F00FFFF);

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