Commit 9021c317 authored by Laurentiu Palcu's avatar Laurentiu Palcu Committed by Lucas Stach
Browse files

drm/imx: Add initial support for DCSS on iMX8MQ 

This adds initial support for iMX8MQ's Display Controller Subsystem (DCSS).
Some of its capabilities include:
 * 4K@60fps;
 * HDR10;
 * one graphics and 2 video pipelines;
 * on-the-fly decompression of compressed video and graphics;

The reference manual can be found here:
https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM



The current patch adds only basic functionality: one primary plane for
graphics, linear, tiled and super-tiled buffers support (no graphics
decompression yet), no HDR10 and no video planes.

Video planes support and HDR10 will be added in subsequent patches once
per-plane de-gamma/CSC/gamma support is in.

Signed-off-by: default avatarLaurentiu Palcu <laurentiu.palcu@nxp.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Acked-by: default avatarGuido Günther <agx@sigxcpu.org>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20200731081836.3048-3-laurentiu.palcu@oss.nxp.com
parent ce625f45

drivers/gpu/drm/imx/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -39,3 +39,5 @@ config DRM_IMX_HDMI 
	depends on DRM_IMX

	help

	  Choose this if you want to use HDMI on i.MX6.



source "drivers/gpu/drm/imx/dcss/Kconfig"

drivers/gpu/drm/imx/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o 
obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o



obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o

obj-$(CONFIG_DRM_IMX_DCSS) += dcss/

drivers/gpu/drm/imx/dcss/Kconfig

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+9 −0
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config DRM_IMX_DCSS

	tristate "i.MX8MQ DCSS"

	select IMX_IRQSTEER

	select DRM_KMS_CMA_HELPER

	select VIDEOMODE_HELPERS

	depends on DRM && ARCH_MXC

	help

	  Choose this if you have a NXP i.MX8MQ based system and want to use the

	  Display Controller Subsystem. This option enables DCSS support.

drivers/gpu/drm/imx/dcss/Makefile

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+6 −0
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imx-dcss-objs := dcss-drv.o dcss-dev.o dcss-blkctl.o dcss-ctxld.o dcss-dtg.o \

				 dcss-ss.o dcss-dpr.o dcss-scaler.o dcss-kms.o dcss-crtc.o \

				 dcss-plane.o



obj-$(CONFIG_DRM_IMX_DCSS) += imx-dcss.o

drivers/gpu/drm/imx/dcss/dcss-blkctl.c

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+70 −0
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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright 2019 NXP.

 */



#include <linux/device.h>

#include <linux/of.h>

#include <linux/slab.h>



#include "dcss-dev.h"



#define DCSS_BLKCTL_RESET_CTRL		0x00

#define   B_CLK_RESETN			BIT(0)

#define   APB_CLK_RESETN		BIT(1)

#define   P_CLK_RESETN			BIT(2)

#define   RTR_CLK_RESETN		BIT(4)

#define DCSS_BLKCTL_CONTROL0		0x10

#define   HDMI_MIPI_CLK_SEL		BIT(0)

#define   DISPMIX_REFCLK_SEL_POS	4

#define   DISPMIX_REFCLK_SEL_MASK	GENMASK(5, 4)

#define   DISPMIX_PIXCLK_SEL		BIT(8)

#define   HDMI_SRC_SECURE_EN		BIT(16)



struct dcss_blkctl {

	struct dcss_dev *dcss;

	void __iomem *base_reg;

};



void dcss_blkctl_cfg(struct dcss_blkctl *blkctl)

{

	if (blkctl->dcss->hdmi_output)

		dcss_writel(0, blkctl->base_reg + DCSS_BLKCTL_CONTROL0);

	else

		dcss_writel(DISPMIX_PIXCLK_SEL,

			    blkctl->base_reg + DCSS_BLKCTL_CONTROL0);



	dcss_set(B_CLK_RESETN | APB_CLK_RESETN | P_CLK_RESETN | RTR_CLK_RESETN,

		 blkctl->base_reg + DCSS_BLKCTL_RESET_CTRL);

}



int dcss_blkctl_init(struct dcss_dev *dcss, unsigned long blkctl_base)

{

	struct dcss_blkctl *blkctl;



	blkctl = kzalloc(sizeof(*blkctl), GFP_KERNEL);

	if (!blkctl)

		return -ENOMEM;



	blkctl->base_reg = ioremap(blkctl_base, SZ_4K);

	if (!blkctl->base_reg) {

		dev_err(dcss->dev, "unable to remap BLK CTRL base\n");

		kfree(blkctl);

		return -ENOMEM;

	}



	dcss->blkctl = blkctl;

	blkctl->dcss = dcss;



	dcss_blkctl_cfg(blkctl);



	return 0;

}



void dcss_blkctl_exit(struct dcss_blkctl *blkctl)

{

	if (blkctl->base_reg)

		iounmap(blkctl->base_reg);



	kfree(blkctl);

}

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