Commit 90105ae1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-fixes-v5.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull iommu fixes from Joerg Roedel:

 - Fixes for page-table issues on Mali GPUs

 - Missing free in an error path for ARM-SMMU

 - PASID decoding in the AMD IOMMU Event log code

 - Another update for the locking fixes in the AMD IOMMU driver

 - Reduce the calls to platform_get_irq() in the IPMMU-VMSA and Rockchip
   IOMMUs to get rid of the warning message added to this function
   recently

* tag 'iommu-fixes-v5.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  iommu/amd: Check PM_LEVEL_SIZE() condition in locked section
  iommu/amd: Fix incorrect PASID decoding from event log
  iommu/ipmmu-vmsa: Only call platform_get_irq() when interrupt is mandatory
  iommu/rockchip: Don't use platform_get_irq to implicitly count irqs
  iommu/io-pgtable-arm: Support all Mali configurations
  iommu/io-pgtable-arm: Correct Mali attributes
  iommu/arm-smmu: Free context bitmap in the err path of arm_smmu_init_domain_context
parents 8eb4b3b0 46ac18c3

drivers/iommu/amd_iommu.c

+7 −5
Original line number Diff line number Diff line
@@ -583,7 +583,8 @@ static void iommu_print_event(struct amd_iommu *iommu, void *__evt) 
retry:

	type    = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;

	devid   = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;

	pasid   = PPR_PASID(*(u64 *)&event[0]);

	pasid   = (event[0] & EVENT_DOMID_MASK_HI) |

		  (event[1] & EVENT_DOMID_MASK_LO);

	flags   = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;

	address = (u64)(((u64)event[3]) << 32) | event[2];
@@ -616,7 +617,7 @@ retry: 
			address, flags);

		break;

	case EVENT_TYPE_PAGE_TAB_ERR:

		dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",

		dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",

			PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),

			pasid, address, flags);

		break;
@@ -1463,6 +1464,7 @@ static void free_pagetable(struct protection_domain *domain) 
 * to 64 bits.

 */

static bool increase_address_space(struct protection_domain *domain,

				   unsigned long address,

				   gfp_t gfp)

{

	unsigned long flags;
@@ -1471,8 +1473,8 @@ static bool increase_address_space(struct protection_domain *domain, 


	spin_lock_irqsave(&domain->lock, flags);



	if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))

		/* address space already 64 bit large */

	if (address <= PM_LEVEL_SIZE(domain->mode) ||

	    WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))

		goto out;



	pte = (void *)get_zeroed_page(gfp);
@@ -1505,7 +1507,7 @@ static u64 *alloc_pte(struct protection_domain *domain, 
	BUG_ON(!is_power_of_2(page_size));



	while (address > PM_LEVEL_SIZE(domain->mode))

		*updated = increase_address_space(domain, gfp) || *updated;

		*updated = increase_address_space(domain, address, gfp) || *updated;



	level   = domain->mode - 1;

	pte     = &domain->pt_root[PM_LEVEL_INDEX(level, address)];

drivers/iommu/amd_iommu_types.h

+2 −2
Original line number Diff line number Diff line
@@ -130,8 +130,8 @@ 
#define EVENT_TYPE_INV_PPR_REQ	0x9

#define EVENT_DEVID_MASK	0xffff

#define EVENT_DEVID_SHIFT	0

#define EVENT_DOMID_MASK	0xffff

#define EVENT_DOMID_SHIFT	0

#define EVENT_DOMID_MASK_LO	0xffff

#define EVENT_DOMID_MASK_HI	0xf0000

#define EVENT_FLAGS_MASK	0xfff

#define EVENT_FLAGS_SHIFT	0x10

drivers/iommu/arm-smmu.c

+1 −0
Original line number Diff line number Diff line
@@ -812,6 +812,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, 
	return 0;



out_clear_smmu:

	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);

	smmu_domain->smmu = NULL;

out_unlock:

	mutex_unlock(&smmu_domain->init_mutex);

drivers/iommu/io-pgtable-arm.c

+45 −13
Original line number Diff line number Diff line
@@ -166,6 +166,9 @@ 
#define ARM_MALI_LPAE_TTBR_READ_INNER	BIT(2)

#define ARM_MALI_LPAE_TTBR_SHARE_OUTER	BIT(4)



#define ARM_MALI_LPAE_MEMATTR_IMP_DEF	0x88ULL

#define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL



/* IOPTE accessors */

#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
@@ -1015,27 +1018,56 @@ arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) 
static struct io_pgtable *

arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)

{

	struct io_pgtable *iop;

	struct arm_lpae_io_pgtable *data;



	if (cfg->ias != 48 || cfg->oas > 40)

	/* No quirks for Mali (hopefully) */

	if (cfg->quirks)

		return NULL;



	if (cfg->ias > 48 || cfg->oas > 40)

		return NULL;



	cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);

	iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);

	if (iop) {

		u64 mair, ttbr;



		/* Copy values as union fields overlap */

		mair = cfg->arm_lpae_s1_cfg.mair[0];

		ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];

	data = arm_lpae_alloc_pgtable(cfg);

	if (!data)

		return NULL;



	/* Mali seems to need a full 4-level table regardless of IAS */

	if (data->levels < ARM_LPAE_MAX_LEVELS) {

		data->levels = ARM_LPAE_MAX_LEVELS;

		data->pgd_size = sizeof(arm_lpae_iopte);

	}

	/*

	 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the

	 * best we can do is mimic the out-of-tree driver and hope that the

	 * "implementation-defined caching policy" is good enough. Similarly,

	 * we'll use it for the sake of a valid attribute for our 'device'

	 * index, although callers should never request that in practice.

	 */

	cfg->arm_mali_lpae_cfg.memattr =

		(ARM_MALI_LPAE_MEMATTR_IMP_DEF

		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |

		(ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC

		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |

		(ARM_MALI_LPAE_MEMATTR_IMP_DEF

		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));



	data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);

	if (!data->pgd)

		goto out_free_data;



	/* Ensure the empty pgd is visible before TRANSTAB can be written */

	wmb();



		cfg->arm_mali_lpae_cfg.memattr = mair;

		cfg->arm_mali_lpae_cfg.transtab = ttbr |

	cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |

					  ARM_MALI_LPAE_TTBR_READ_INNER |

					  ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;

	}

	return &data->iop;



	return iop;

out_free_data:

	kfree(data);

	return NULL;

}



struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {

drivers/iommu/ipmmu-vmsa.c

+1 −2
Original line number Diff line number Diff line
@@ -1086,8 +1086,6 @@ static int ipmmu_probe(struct platform_device *pdev) 


	mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts);



	irq = platform_get_irq(pdev, 0);



	/*

	 * Determine if this IPMMU instance is a root device by checking for

	 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
@@ -1106,6 +1104,7 @@ static int ipmmu_probe(struct platform_device *pdev) 


	/* Root devices have mandatory IRQs */

	if (ipmmu_is_root(mmu)) {

		irq = platform_get_irq(pdev, 0);

		if (irq < 0) {

			dev_err(&pdev->dev, "no IRQ found\n");

			return irq;

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