microblaze: Improve checking mechanism for MSR instruction (9002062f) · Commits · 戴 / test

arch/microblaze/kernel/head.S

+5 −8

Original line number	Diff line number	Diff line
		@@ -54,19 +54,16 @@ ENTRY(_start)
		mfs r1, rmsr
		andi r1, r1, ~2
		mts rmsr, r1

		/*
		* Here is checking mechanism which check if Microblaze has msr instructions
		* We load msr and compare it with previous r1 value - if is the same,
		* msr instructions works if not - cpu don't have them.
		*/
		or r8, r0, r0 /* 0 - I have msr instr, 1 - I don't have */
		or r12, r0, r0
		msrset r12, 0 /* set nothing - just read msr for test */
		cmpu r12, r12, r1
		beqi r12, 1f
		ori r8, r0, 1 /* I don't have msr */
		1:
		/* r8=0 - I have msr instr, 1 - I don't have them */
		rsubi r0, r0, 1 /* set the carry bit */
		msrclr r0, 0x4 /* try to clear it */
		/* read the carry bit, r8 will be '0' if msrclr exists */
		addik r8, r0, 0

		/* r7 may point to an FDT, or there may be one linked in.
		if it's in r7, we've got to save it away ASAP.