Commit 9001b176 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2020-03-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



UAPI Changes:

On i915 we have a new UAPI to allow userspace to specify CS ring buffer size on
construction (I915_CONTEXT_PARAM_RINGSIZE) and also new sysfs entries exposing
various engine properties

GVT Changes:

VFIO edid getting expanded to all platforms and a big cleanup around attr
group, unused vblank complete, kvmgt, Intel engine and dev_priv usages.

i915 Changes:

- new UAPI to allow userspace to specify CS ring buffer size on construction
  (I915_CONTEXT_PARAM_RINGSIZE) -  (Chris)
- New sysfs entries exposing various engine properties (Chris)
- Tiger Lake is out of require_force_probe protection (Jose)
- Changes in many places around active requests, reset and heartbeat (Chris)
- Stop assigning drm-dev_private pointer (Jani)
- Many code refactor in many places, including intel_modeset_init,
  increasing use of intel_uncore_*, vgpu, and gvt stuff (Jani)
- Fixes around display pipe iterators (Anshuman)
- Tigerlake enabling work (Matt Ropper, Matt Atwood, Ville, Lucas, Daniele,
  Jose, Anusha, Vivek, Swathi, Caz. Kai)
- Code clean-up like reducing use of drm/i915_drv.h, removing unused
  registers, removing garbage warns, and some other code polishing (Jani, Lucas,
  Ville)
- Selftests fixes, improvements and additions (Chris, Dan, Aditya, Matt Auld)
- Fix plane possible_crtcs bit mask (Anshuman)
- Fixes and cleanup on GLK pre production identification and w/a (Ville)
- Fix display orientation on few cases (Hans, Ville)
- dbuf clean-up and improvements for slice arrays handling (Ville)
- Improvement around min cdclk calculation (Stanislav)
- Fixes and refactor around display PLLs (Imre)
- Other execlists and perf fixes (Chris)
- Documentation fixes (Jani, Chris)
- Fix build issue (Anshuman)
- Many more fixes around the locking mechanisms (Chris)
- Other fixes and debugability info around preemption (Chris, Tvrtko)
- Add mechanism to submit a context WA on ring submission (Mika)
- Clear all Eu/L3 resitual context (Prathap)
- More changes around local memory (Abdiel, Matt, Chris)
- Fix RPS (Chris)
- DP MST fix (Lyude)
- Display FBC fixes (Jose, RK)
- debugfs cleanup (Tvrtko)
- More convertion towards drm_debive based loggin (Wambui, Ram)
- Avoid potential buffer overflow (Takashi)
- Ice Lake and Elkhart Lake workarounds (Matt Roper)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200314001535.GA2969344@intel.com
parents bda1fb0e 217a485c

Documentation/gpu/i915.rst

+4 −4
Original line number Diff line number Diff line
@@ -207,10 +207,10 @@ DPIO 
CSR firmware support for DMC

----------------------------



.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c

   :doc: csr support for dmc



.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c

   :internal:



Video BIOS Table (VBT)
@@ -332,7 +332,7 @@ This process is dubbed relocation. 
GEM BO Management Implementation Details

----------------------------------------



.. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h

.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h

   :doc: Virtual Memory Address



Buffer Object Eviction
@@ -382,7 +382,7 @@ Logical Rings, Logical Ring Contexts and Execlists 
Global GTT views

----------------



.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c

.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h

   :doc: Global GTT views



.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c

drivers/gpu/drm/drm_dp_helper.c

+79 −0
Original line number Diff line number Diff line
@@ -1280,6 +1280,85 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 
#undef DEVICE_ID_ANY

#undef DEVICE_ID



struct edid_quirk {

	u8 mfg_id[2];

	u8 prod_id[2];

	u32 quirks;

};



#define MFG(first, second) { (first), (second) }

#define PROD_ID(first, second) { (first), (second) }



/*

 * Some devices have unreliable OUIDs where they don't set the device ID

 * correctly, and as a result we need to use the EDID for finding additional

 * DP quirks in such cases.

 */

static const struct edid_quirk edid_quirk_list[] = {

	/* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation

	 * only supports DPCD backlight controls

	 */

	{ MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	/*

	 * Some Dell CML 2020 systems have panels support both AUX and PWM

	 * backlight control, and some only support AUX backlight control. All

	 * said panels start up in AUX mode by default, and we don't have any

	 * support for disabling HDR mode on these panels which would be

	 * required to switch to PWM backlight control mode (plus, I'm not

	 * even sure we want PWM backlight controls over DPCD backlight

	 * controls anyway...). Until we have a better way of detecting these,

	 * force DPCD backlight mode on all of them.

	 */

	{ MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

	{ MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },

};



#undef MFG

#undef PROD_ID



/**

 * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional

 * DP-specific quirks

 * @edid: The EDID to check

 *

 * While OUIDs are meant to be used to recognize a DisplayPort device, a lot

 * of manufacturers don't seem to like following standards and neglect to fill

 * the dev-ID in, making it impossible to only use OUIDs for determining

 * quirks in some cases. This function can be used to check the EDID and look

 * up any additional DP quirks. The bits returned by this function correspond

 * to the quirk bits in &drm_dp_quirk.

 *

 * Returns: a bitmask of quirks, if any. The driver can check this using

 * drm_dp_has_quirk().

 */

u32 drm_dp_get_edid_quirks(const struct edid *edid)

{

	const struct edid_quirk *quirk;

	u32 quirks = 0;

	int i;



	if (!edid)

		return 0;



	for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {

		quirk = &edid_quirk_list[i];

		if (memcmp(quirk->mfg_id, edid->mfg_id,

			   sizeof(edid->mfg_id)) == 0 &&

		    memcmp(quirk->prod_id, edid->prod_code,

			   sizeof(edid->prod_code)) == 0)

			quirks |= quirk->quirks;

	}



	DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n",

		      (int)sizeof(edid->mfg_id), edid->mfg_id,

		      (int)sizeof(edid->prod_code), edid->prod_code, quirks);



	return quirks;

}

EXPORT_SYMBOL(drm_dp_get_edid_quirks);



/**

 * drm_dp_read_desc - read sink/branch descriptor from DPCD

 * @aux: DisplayPort AUX channel

drivers/gpu/drm/drm_dp_mst_topology.c

+2 −1
Original line number Diff line number Diff line
@@ -5472,7 +5472,8 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port) 
	if (drm_dp_read_desc(port->mgr->aux, &desc, true))

		return NULL;



	if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&

	if (drm_dp_has_quirk(&desc, 0,

			     DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) &&

	    port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 &&

	    port->parent == port->mgr->mst_primary) {

		u8 downstreamport;

drivers/gpu/drm/i915/Kconfig.profile

+22 −3
Original line number Diff line number Diff line
@@ -20,6 +20,9 @@ config DRM_I915_HEARTBEAT_INTERVAL 
	  check the health of the GPU and undertake regular house-keeping of

	  internal driver state.



	  This is adjustable via

	  /sys/class/drm/card?/engine/*/heartbeat_interval_ms



	  May be 0 to disable heartbeats and therefore disable automatic GPU

	  hang detection.
@@ -33,11 +36,18 @@ config DRM_I915_PREEMPT_TIMEOUT 
	  expires, the HW will be reset to allow the more important context

	  to execute.



	  This is adjustable via

	  /sys/class/drm/card?/engine/*/preempt_timeout_ms



	  May be 0 to disable the timeout.



config DRM_I915_SPIN_REQUEST

	int "Busywait for request completion (us)"

	default 5 # microseconds

	  The compiled in default may get overridden at driver probe time on

	  certain platforms and certain engines which will be reflected in the

	  sysfs control.



config DRM_I915_MAX_REQUEST_BUSYWAIT

	int "Busywait for request completion limit (ns)"

	default 8000 # nanoseconds

	help

	  Before sleeping waiting for a request (GPU operation) to complete,

	  we may spend some time polling for its completion. As the IRQ may
@@ -45,6 +55,9 @@ config DRM_I915_SPIN_REQUEST 
	  check if the request will complete in the time it would have taken

	  us to enable the interrupt.



	  This is adjustable via

	  /sys/class/drm/card?/engine/*/max_busywait_duration_ns



	  May be 0 to disable the initial spin. In practice, we estimate

	  the cost of enabling the interrupt (if currently disabled) to be

	  a few microseconds.
@@ -60,6 +73,9 @@ config DRM_I915_STOP_TIMEOUT 
	  that the reset itself may take longer and so be more disruptive to

	  interactive or low latency workloads.



	  This is adjustable via

	  /sys/class/drm/card?/engine/*/stop_timeout_ms



config DRM_I915_TIMESLICE_DURATION

	int "Scheduling quantum for userspace batches (ms, jiffy granularity)"

	default 1 # milliseconds
@@ -73,4 +89,7 @@ config DRM_I915_TIMESLICE_DURATION 
	  is scheduled for execution for the timeslice duration, before

	  switching to the next context.



	  This is adjustable via

	  /sys/class/drm/card?/engine/*/timeslice_duration_ms



	  May be 0 to disable timeslicing.

drivers/gpu/drm/i915/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ i915-y += i915_drv.o \ 
	  i915_sysfs.o \

	  i915_utils.o \

	  intel_device_info.o \

	  intel_dram.o \

	  intel_memory_region.o \

	  intel_pch.o \

	  intel_pm.o \
@@ -79,9 +80,11 @@ gt-y += \ 
	gt/debugfs_gt.o \

	gt/debugfs_gt_pm.o \

	gt/gen6_ppgtt.o \

	gt/gen7_renderclear.o \

	gt/gen8_ppgtt.o \

	gt/intel_breadcrumbs.o \

	gt/intel_context.o \

	gt/intel_context_param.o \

	gt/intel_context_sseu.o \

	gt/intel_engine_cs.o \

	gt/intel_engine_heartbeat.o \
@@ -107,7 +110,8 @@ gt-y += \ 
	gt/intel_rps.o \

	gt/intel_sseu.o \

	gt/intel_timeline.o \

	gt/intel_workarounds.o

	gt/intel_workarounds.o \

	gt/sysfs_engines.o

# autogenerated null render state

gt-y += \

	gt/gen6_renderstate.o \

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