Commit 8ff1f792 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.7' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Alex writes:
"The big changes for 3.7 include:
- Asynchronous VM page table updates for Cayman/SI
- 2 level VM page table support.  Saves memory compared to 1 level
  page tables.
- Reworked PLL handing in the display code allows lots more
  combinations of monitors to work, including more than two
  DP displays assuming compatible clocks across shared PLLs.
  This also allows us to power down extra PLLs when we can
  share a single one across multiple displays which saves power.
- Native backlight control on ATOMBIOS systems.
- Improved ACPI support for interacting with the GPU.  Fixes
  backlight control on some laptops.
- Document AMD ACPI interfaces
- Lots of code cleanup
- Bug fixes"

* 'drm-next-3.7' of git://people.freedesktop.org/~agd5f/linux: (79 commits)
  drm/radeon: add vm set_page() callback for SI
  drm/radeon: rework the vm_flush interface
  drm/radeon: use WRITE_DATA packets for vm flush on SI
  drm/radeon/pm: fix multi-head profile handling on BTC+ (v2)
  drm/radeon: fix radeon power state debug output
  drm/radeon: force MSIs on RS690 asics
  drm/radeon: Add MSI quirk for gateway RS690
  drm/radeon: allow MIP_ADDRESS=0 for MSAA textures on Evergreen
  drm/radeon/kms: allow STRMOUT_BASE_UPDATE on RS780 and RS880
  drm/radeon: add 2-level VM pagetables support v9
  drm/radeon: refactor set_page chipset interface v5
  drm/radeon: Fix scratch register leak in IB test.
  drm/radeon: restore backlight level on resume
  drm/radeon: add get_backlight_level callback
  drm/radeon: only adjust default clocks on NI GPUs
  drm/radeon: validate PPLL in crtc fixup
  drm/radeon: work around KMS modeset limitations in PLL allocation (v2)
  drm/radeon: make non-DP PPLL sharing more robust
  drm/radeon: store the encoder in the radeon_crtc
  drm/radeon: rework crtc pll setup to better support PPLL sharing
  ...
parents 2216c9e7 82ffd92b

drivers/acpi/video.c

+4 −4
Original line number Diff line number Diff line
@@ -1448,7 +1448,6 @@ static void acpi_video_bus_notify(struct acpi_device *device, u32 event) 
	case ACPI_VIDEO_NOTIFY_SWITCH:	/* User requested a switch,

					 * most likely via hotkey. */

		acpi_bus_generate_proc_event(device, event, 0);

		if (!acpi_notifier_call_chain(device, event, 0))

		keycode = KEY_SWITCHVIDEOMODE;

		break;
@@ -1479,8 +1478,9 @@ static void acpi_video_bus_notify(struct acpi_device *device, u32 event) 
		break;

	}



	if (event != ACPI_VIDEO_NOTIFY_SWITCH)

		acpi_notifier_call_chain(device, event, 0);

	if (acpi_notifier_call_chain(device, event, 0))

		/* Something vetoed the keypress. */

		keycode = 0;



	if (keycode) {

		input_report_key(input, keycode, 1);

drivers/gpu/drm/radeon/atombios_crtc.c

+428 −235

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/atombios_encoders.c

+285 −82
Original line number Diff line number Diff line
@@ -28,9 +28,251 @@ 
#include "radeon_drm.h"

#include "radeon.h"

#include "atom.h"

#include <linux/backlight.h>



extern int atom_debug;



static u8

radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)

{

	u8 backlight_level;

	u32 bios_2_scratch;



	if (rdev->family >= CHIP_R600)

		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);

	else

		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);



	backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>

			   ATOM_S2_CURRENT_BL_LEVEL_SHIFT);



	return backlight_level;

}



static void

radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,

				       u8 backlight_level)

{

	u32 bios_2_scratch;



	if (rdev->family >= CHIP_R600)

		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);

	else

		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);



	bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;

	bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &

			   ATOM_S2_CURRENT_BL_LEVEL_MASK);



	if (rdev->family >= CHIP_R600)

		WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);

	else

		WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);

}



u8

atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)

{

	struct drm_device *dev = radeon_encoder->base.dev;

	struct radeon_device *rdev = dev->dev_private;



	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))

		return 0;



	return radeon_atom_get_backlight_level_from_reg(rdev);

}



void

atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)

{

	struct drm_encoder *encoder = &radeon_encoder->base;

	struct drm_device *dev = radeon_encoder->base.dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder_atom_dig *dig;

	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;

	int index;



	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))

		return;



	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&

	    radeon_encoder->enc_priv) {

		dig = radeon_encoder->enc_priv;

		dig->backlight_level = level;

		radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);



		switch (radeon_encoder->encoder_id) {

		case ENCODER_OBJECT_ID_INTERNAL_LVDS:

		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:

			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);

			if (dig->backlight_level == 0) {

				args.ucAction = ATOM_LCD_BLOFF;

				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

			} else {

				args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;

				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

				args.ucAction = ATOM_LCD_BLON;

				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);

			}

			break;

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

			if (dig->backlight_level == 0)

				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);

			else {

				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);

				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);

			}

			break;

		default:

			break;

		}

	}

}



#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)



static u8 radeon_atom_bl_level(struct backlight_device *bd)

{

	u8 level;



	/* Convert brightness to hardware level */

	if (bd->props.brightness < 0)

		level = 0;

	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)

		level = RADEON_MAX_BL_LEVEL;

	else

		level = bd->props.brightness;



	return level;

}



static int radeon_atom_backlight_update_status(struct backlight_device *bd)

{

	struct radeon_backlight_privdata *pdata = bl_get_data(bd);

	struct radeon_encoder *radeon_encoder = pdata->encoder;



	atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));



	return 0;

}



static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)

{

	struct radeon_backlight_privdata *pdata = bl_get_data(bd);

	struct radeon_encoder *radeon_encoder = pdata->encoder;

	struct drm_device *dev = radeon_encoder->base.dev;

	struct radeon_device *rdev = dev->dev_private;



	return radeon_atom_get_backlight_level_from_reg(rdev);

}



static const struct backlight_ops radeon_atom_backlight_ops = {

	.get_brightness = radeon_atom_backlight_get_brightness,

	.update_status	= radeon_atom_backlight_update_status,

};



void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,

				struct drm_connector *drm_connector)

{

	struct drm_device *dev = radeon_encoder->base.dev;

	struct radeon_device *rdev = dev->dev_private;

	struct backlight_device *bd;

	struct backlight_properties props;

	struct radeon_backlight_privdata *pdata;

	struct radeon_encoder_atom_dig *dig;

	u8 backlight_level;



	if (!radeon_encoder->enc_priv)

		return;



	if (!rdev->is_atom_bios)

		return;



	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))

		return;



	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);

	if (!pdata) {

		DRM_ERROR("Memory allocation failed\n");

		goto error;

	}



	memset(&props, 0, sizeof(props));

	props.max_brightness = RADEON_MAX_BL_LEVEL;

	props.type = BACKLIGHT_RAW;

	bd = backlight_device_register("radeon_bl", &drm_connector->kdev,

				       pdata, &radeon_atom_backlight_ops, &props);

	if (IS_ERR(bd)) {

		DRM_ERROR("Backlight registration failed\n");

		goto error;

	}



	pdata->encoder = radeon_encoder;



	backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);



	dig = radeon_encoder->enc_priv;

	dig->bl_dev = bd;



	bd->props.brightness = radeon_atom_backlight_get_brightness(bd);

	bd->props.power = FB_BLANK_UNBLANK;

	backlight_update_status(bd);



	DRM_INFO("radeon atom DIG backlight initialized\n");



	return;



error:

	kfree(pdata);

	return;

}



static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)

{

	struct drm_device *dev = radeon_encoder->base.dev;

	struct radeon_device *rdev = dev->dev_private;

	struct backlight_device *bd = NULL;

	struct radeon_encoder_atom_dig *dig;



	if (!radeon_encoder->enc_priv)

		return;



	if (!rdev->is_atom_bios)

		return;



	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))

		return;



	dig = radeon_encoder->enc_priv;

	bd = dig->bl_dev;

	dig->bl_dev = NULL;



	if (bd) {

		struct radeon_legacy_backlight_privdata *pdata;



		pdata = bl_get_data(bd);

		backlight_device_unregister(bd);

		kfree(pdata);



		DRM_INFO("radeon atom LVDS backlight unloaded\n");

	}

}



#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */



void radeon_atom_backlight_init(struct radeon_encoder *encoder)

{

}



static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)

{

}



#endif



/* evil but including atombios.h is much worse */

bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,

				struct drm_display_mode *mode);
@@ -209,6 +451,32 @@ atombios_tv_setup(struct drm_encoder *encoder, int action) 


}



static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)

{

	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

	int bpc = 8;



	if (connector)

		bpc = radeon_get_monitor_bpc(connector);



	switch (bpc) {

	case 0:

		return PANEL_BPC_UNDEFINE;

	case 6:

		return PANEL_6BIT_PER_COLOR;

	case 8:

	default:

		return PANEL_8BIT_PER_COLOR;

	case 10:

		return PANEL_10BIT_PER_COLOR;

	case 12:

		return PANEL_12BIT_PER_COLOR;

	case 16:

		return PANEL_16BIT_PER_COLOR;

	}

}





union dvo_encoder_control {

	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;

	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
@@ -406,7 +674,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) 
		return ATOM_ENCODER_MODE_DP;



	/* DVO is always DVO */

	if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)

	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||

	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))

		return ATOM_ENCODER_MODE_DVO;



	connector = radeon_get_connector_for_encoder(encoder);
@@ -535,7 +804,6 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo 
	int dp_clock = 0;

	int dp_lane_count = 0;

	int hpd_id = RADEON_HPD_NONE;

	int bpc = 8;



	if (connector) {

		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -545,7 +813,6 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo 
		dp_clock = dig_connector->dp_clock;

		dp_lane_count = dig_connector->dp_lane_count;

		hpd_id = radeon_connector->hpd.hpd;

		bpc = radeon_get_monitor_bpc(connector);

	}



	/* no dig encoder assigned */
@@ -612,37 +879,17 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo 
			else

				args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);



			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))

			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))

				args.v3.ucLaneNum = dp_lane_count;

			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))

				args.v3.ucLaneNum = 8;

			else

				args.v3.ucLaneNum = 4;



			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))

			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))

				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;

			args.v3.acConfig.ucDigSel = dig->dig_encoder;

			switch (bpc) {

			case 0:

				args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;

				break;

			case 6:

				args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;

				break;

			case 8:

			default:

				args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;

				break;

			case 10:

				args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;

				break;

			case 12:

				args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;

				break;

			case 16:

				args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;

				break;

			}

			args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);

			break;

		case 4:

			args.v4.ucAction = action;
@@ -652,41 +899,21 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo 
			else

				args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);



			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))

			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))

				args.v4.ucLaneNum = dp_lane_count;

			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))

				args.v4.ucLaneNum = 8;

			else

				args.v4.ucLaneNum = 4;



			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {

			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {

				if (dp_clock == 270000)

					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;

				else if (dp_clock == 540000)

					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;

			}

			args.v4.acConfig.ucDigSel = dig->dig_encoder;

			switch (bpc) {

			case 0:

				args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;

				break;

			case 6:

				args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;

				break;

			case 8:

			default:

				args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;

				break;

			case 10:

				args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;

				break;

			case 12:

				args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;

				break;

			case 16:

				args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;

				break;

			}

			args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);

			if (hpd_id == RADEON_HPD_NONE)

				args.v4.ucHPD_ID = 0;

			else
@@ -799,8 +1026,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t 
				args.v1.asMode.ucLaneSet = lane_set;

			} else {

				if (is_dp)

					args.v1.usPixelClock =

						cpu_to_le16(dp_clock / 10);

					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);

				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))

					args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);

				else
@@ -857,8 +1083,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t 
				args.v2.asMode.ucLaneSet = lane_set;

			} else {

				if (is_dp)

					args.v2.usPixelClock =

						cpu_to_le16(dp_clock / 10);

					args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);

				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))

					args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);

				else
@@ -900,8 +1125,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t 
				args.v3.asMode.ucLaneSet = lane_set;

			} else {

				if (is_dp)

					args.v3.usPixelClock =

						cpu_to_le16(dp_clock / 10);

					args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);

				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))

					args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);

				else
@@ -960,8 +1184,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t 
				args.v4.asMode.ucLaneSet = lane_set;

			} else {

				if (is_dp)

					args.v4.usPixelClock =

						cpu_to_le16(dp_clock / 10);

					args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);

				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))

					args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);

				else
@@ -1147,7 +1370,6 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, 
	int dp_lane_count = 0;

	int connector_object_id = 0;

	u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;

	int bpc = 8;



	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)

		connector = radeon_get_connector_for_encoder_init(encoder);
@@ -1163,7 +1385,6 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, 
		dp_lane_count = dig_connector->dp_lane_count;

		connector_object_id =

			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;

		bpc = radeon_get_monitor_bpc(connector);

	}



	memset(&args, 0, sizeof(args));
@@ -1221,27 +1442,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, 
				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;

				break;

			}

			switch (bpc) {

			case 0:

				args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;

				break;

			case 6:

				args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;

				break;

			case 8:

			default:

				args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;

				break;

			case 10:

				args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;

				break;

			case 12:

				args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;

				break;

			case 16:

				args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;

				break;

			}

			args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);

			break;

		default:

			DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
@@ -2286,6 +2487,8 @@ static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 
void radeon_enc_destroy(struct drm_encoder *encoder)

{

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))

		radeon_atom_backlight_exit(radeon_encoder);

	kfree(radeon_encoder->enc_priv);

	drm_encoder_cleanup(encoder);

	kfree(radeon_encoder);
@@ -2295,7 +2498,7 @@ static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 
	.destroy = radeon_enc_destroy,

};



struct radeon_encoder_atom_dac *

static struct radeon_encoder_atom_dac *

radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)

{

	struct drm_device *dev = radeon_encoder->base.dev;
@@ -2309,7 +2512,7 @@ radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 
	return dac;

}



struct radeon_encoder_atom_dig *

static struct radeon_encoder_atom_dig *

radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)

{

	int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;

drivers/gpu/drm/radeon/evergreen.c

+161 −121

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/evergreen_cs.c

+53 −8
Original line number Diff line number Diff line
@@ -846,6 +846,16 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, 
		return -EINVAL;

	}



	if (!mipmap) {

		if (llevel) {

			dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n",

				 __func__, __LINE__);

			return -EINVAL;

		} else {

			return 0; /* everything's ok */

		}

	}



	/* check mipmap size */

	for (i = 1; i <= llevel; i++) {

		unsigned w, h, d;
@@ -995,7 +1005,7 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p) 
 * Assume that chunk_ib_index is properly set. Will return -EINVAL

 * if packet is bigger than remaining ib size. or if packets is unknown.

 **/

int evergreen_cs_packet_parse(struct radeon_cs_parser *p,

static int evergreen_cs_packet_parse(struct radeon_cs_parser *p,

			      struct radeon_cs_packet *pkt,

			      unsigned idx)

{
@@ -1080,6 +1090,27 @@ static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 
	return 0;

}



/**

 * evergreen_cs_packet_next_is_pkt3_nop() - test if the next packet is NOP

 * @p:		structure holding the parser context.

 *

 * Check if the next packet is a relocation packet3.

 **/

static bool evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)

{

	struct radeon_cs_packet p3reloc;

	int r;



	r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);

	if (r) {

		return false;

	}

	if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {

		return false;

	}

	return true;

}



/**

 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet

 * @parser:		parser structure holding parsing context.
@@ -2330,7 +2361,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
		for (i = 0; i < (pkt->count / 8); i++) {

			struct radeon_bo *texture, *mipmap;

			u32 toffset, moffset;

			u32 size, offset;

			u32 size, offset, mip_address, tex_dim;



			switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {

			case SQ_TEX_VTX_VALID_TEXTURE:
@@ -2359,7 +2390,19 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
				}

				texture = reloc->robj;

				toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);



				/* tex mip base */

				tex_dim = ib[idx+1+(i*8)+0] & 0x7;

				mip_address = ib[idx+1+(i*8)+3];



				if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&

				    !mip_address &&

				    !evergreen_cs_packet_next_is_pkt3_nop(p)) {

					/* MIP_ADDRESS should point to FMASK for an MSAA texture.

					 * It should be 0 if FMASK is disabled. */

					moffset = 0;

					mipmap = NULL;

				} else {

					r = evergreen_cs_packet_next_reloc(p, &reloc);

					if (r) {

						DRM_ERROR("bad SET_RESOURCE (tex)\n");
@@ -2367,6 +2410,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
					}

					moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);

					mipmap = reloc->robj;

				}



				r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));

				if (r)

					return r;

CRA Git | Maintained and supported by SUSTech CRA and CCSE