ARM: 7787/1: virt: ensure visibility of __boot_cpu_mode (8fbac214) · Commits · 戴 / test

Secondary CPUs write to __boot_cpu_mode with caches disabled, and thus a cached value of __boot_cpu_mode may be incoherent with that in memory. This could lead to a failure to detect mismatched boot modes. This patch adds flushing to ensure that writes by secondaries to __boot_cpu_mode are made visible before we test against it. Signed-off-by:

Mark Rutland <mark.rutland@arm.com> Acked-by:

Dave Martin <Dave.Martin@arm.com> Acked-by:

Marc Zyngier <marc.zyngier@arm.com> Cc: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/include/asm/virt.h

+12 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@
		#define BOOT_CPU_MODE_MISMATCH PSR_N_BIT

		#ifndef __ASSEMBLY__
		#include <asm/cacheflush.h>

		#ifdef CONFIG_ARM_VIRT_EXT
		/*
		@@ -41,10 +42,21 @@
		*/
		extern int __boot_cpu_mode;

		static inline void sync_boot_mode(void)
		{
		/*
		* As secondaries write to __boot_cpu_mode with caches disabled, we
		* must flush the corresponding cache entries to ensure the visibility
		* of their writes.
		*/
		sync_cache_r(&__boot_cpu_mode);
		}

		void __hyp_set_vectors(unsigned long phys_vector_base);
		unsigned long __hyp_get_vectors(void);
		#else
		#define __boot_cpu_mode (SVC_MODE)
		#define sync_boot_mode()
		#endif

		#ifndef ZIMAGE

arch/arm/kernel/setup.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -836,6 +836,8 @@ static int __init meminfo_cmp(const void _a, const void _b)
		void __init hyp_mode_check(void)
		{
		#ifdef CONFIG_ARM_VIRT_EXT
		sync_boot_mode();

		if (is_hyp_mode_available()) {
		pr_info("CPU: All CPU(s) started in HYP mode.\n");
		pr_info("CPU: Virtualization extensions available.\n");

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