Commit 8fb9df97 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'sh_eth-get-rid-of-the-dedicated-regiseter-mapping-for-RZ-A1-R7S72100' 



Sergei Shtylyov says:

====================
sh_eth: get rid of the dedicated regiseter mapping for RZ/A1 (R7S72100)

Here's a set of 5 patches against DaveM's 'net-next.git' repo.

I changed my mind about the RZ/A1 SoC needing its own register
map -- now that we don't depend on the register map array in order
to determine whether a given register exists any more, we can add
a new flag to determine if the GECMR exists (this register is
present only on true GEther chips, not RZ/A1). We also need to
add the sh_eth_cpu_data::* flag checks where they were missing
so far: in the ethtool API for the register dump.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 5652b46e b39b7092

drivers/net/ethernet/renesas/sh_eth.c

+28 −76
Original line number Diff line number Diff line
@@ -142,69 +142,6 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 
	[FWALCR1]	= 0x00b4,

};



static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {

	SH_ETH_OFFSET_DEFAULTS,



	[EDSR]		= 0x0000,

	[EDMR]		= 0x0400,

	[EDTRR]		= 0x0408,

	[EDRRR]		= 0x0410,

	[EESR]		= 0x0428,

	[EESIPR]	= 0x0430,

	[TDLAR]		= 0x0010,

	[TDFAR]		= 0x0014,

	[TDFXR]		= 0x0018,

	[TDFFR]		= 0x001c,

	[RDLAR]		= 0x0030,

	[RDFAR]		= 0x0034,

	[RDFXR]		= 0x0038,

	[RDFFR]		= 0x003c,

	[TRSCER]	= 0x0438,

	[RMFCR]		= 0x0440,

	[TFTR]		= 0x0448,

	[FDR]		= 0x0450,

	[RMCR]		= 0x0458,

	[RPADIR]	= 0x0460,

	[FCFTR]		= 0x0468,

	[CSMR]		= 0x04E4,



	[ECMR]		= 0x0500,

	[RFLR]		= 0x0508,

	[ECSR]		= 0x0510,

	[ECSIPR]	= 0x0518,

	[PIR]		= 0x0520,

	[APR]		= 0x0554,

	[MPR]		= 0x0558,

	[PFTCR]		= 0x055c,

	[PFRCR]		= 0x0560,

	[TPAUSER]	= 0x0564,

	[MAHR]		= 0x05c0,

	[MALR]		= 0x05c8,

	[CEFCR]		= 0x0740,

	[FRECR]		= 0x0748,

	[TSFRCR]	= 0x0750,

	[TLFRCR]	= 0x0758,

	[RFCR]		= 0x0760,

	[MAFCR]		= 0x0778,



	[ARSTR]		= 0x0000,

	[TSU_CTRST]	= 0x0004,

	[TSU_FWSLC]	= 0x0038,

	[TSU_VTAG0]	= 0x0058,

	[TSU_ADSBSY]	= 0x0060,

	[TSU_TEN]	= 0x0064,

	[TSU_POST1]	= 0x0070,

	[TSU_POST2]	= 0x0074,

	[TSU_POST3]	= 0x0078,

	[TSU_POST4]	= 0x007c,

	[TSU_ADRH0]	= 0x0100,



	[TXNLCR0]	= 0x0080,

	[TXALCR0]	= 0x0084,

	[RXNLCR0]	= 0x0088,

	[RXALCR0]	= 0x008C,

};



static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {

	SH_ETH_OFFSET_DEFAULTS,
@@ -569,6 +506,9 @@ static void sh_eth_set_rate_gether(struct net_device *ndev) 
{

	struct sh_eth_private *mdp = netdev_priv(ndev);



	if (WARN_ON(!mdp->cd->gecmr))

		return;



	switch (mdp->speed) {

	case 10: /* 10BASE */

		sh_eth_write(ndev, GECMR_10, GECMR);
@@ -590,7 +530,7 @@ static struct sh_eth_cpu_data r7s72100_data = { 
	.chip_reset	= sh_eth_chip_reset,

	.set_duplex	= sh_eth_set_duplex,



	.register_type	= SH_ETH_REG_FAST_RZ,

	.register_type	= SH_ETH_REG_GIGABIT,



	.edtrr_trns	= EDTRR_TRNS_GETHER,

	.ecsr_value	= ECSR_ICD,
@@ -663,6 +603,7 @@ static struct sh_eth_cpu_data r8a7740_data = { 
	.apr		= 1,

	.mpr		= 1,

	.tpauser	= 1,

	.gecmr		= 1,

	.bculr		= 1,

	.hw_swap	= 1,

	.rpadir		= 1,
@@ -788,6 +729,7 @@ static struct sh_eth_cpu_data r8a77980_data = { 
	.apr		= 1,

	.mpr		= 1,

	.tpauser	= 1,

	.gecmr		= 1,

	.bculr		= 1,

	.hw_swap	= 1,

	.nbst		= 1,
@@ -957,6 +899,9 @@ static void sh_eth_set_rate_giga(struct net_device *ndev) 
{

	struct sh_eth_private *mdp = netdev_priv(ndev);



	if (WARN_ON(!mdp->cd->gecmr))

		return;



	switch (mdp->speed) {

	case 10: /* 10BASE */

		sh_eth_write(ndev, 0x00000000, GECMR);
@@ -1002,6 +947,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = { 
	.apr		= 1,

	.mpr		= 1,

	.tpauser	= 1,

	.gecmr		= 1,

	.bculr		= 1,

	.hw_swap	= 1,

	.rpadir		= 1,
@@ -1042,6 +988,7 @@ static struct sh_eth_cpu_data sh7734_data = { 
	.apr		= 1,

	.mpr		= 1,

	.tpauser	= 1,

	.gecmr		= 1,

	.bculr		= 1,

	.hw_swap	= 1,

	.no_trimd	= 1,
@@ -1083,6 +1030,7 @@ static struct sh_eth_cpu_data sh7763_data = { 
	.apr		= 1,

	.mpr		= 1,

	.tpauser	= 1,

	.gecmr		= 1,

	.bculr		= 1,

	.hw_swap	= 1,

	.no_trimd	= 1,
@@ -2140,10 +2088,12 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 
	add_reg(EESR);

	add_reg(EESIPR);

	add_reg(TDLAR);

	if (!cd->no_xdfar)

		add_reg(TDFAR);

	add_reg(TDFXR);

	add_reg(TDFFR);

	add_reg(RDLAR);

	if (!cd->no_xdfar)

		add_reg(RDFAR);

	add_reg(RDFXR);

	add_reg(RDFFR);
@@ -2179,21 +2129,26 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 
	if (cd->tpauser)

		add_reg(TPAUSER);

	add_reg(TPAUSECR);

	if (cd->gecmr)

		add_reg(GECMR);

	if (cd->bculr)

		add_reg(BCULR);

	add_reg(MAHR);

	add_reg(MALR);

	if (!cd->no_tx_cntrs) {

		add_reg(TROCR);

		add_reg(CDCR);

		add_reg(LCCR);

		add_reg(CNDCR);

	}

	add_reg(CEFCR);

	add_reg(FRECR);

	add_reg(TSFRCR);

	add_reg(TLFRCR);

	if (cd->cexcr) {

		add_reg(CERCR);

		add_reg(CEECR);

	}

	add_reg(MAFCR);

	if (cd->rtrate)

		add_reg(RTRATE);
@@ -3121,9 +3076,6 @@ static const u16 *sh_eth_get_register_offset(int register_type) 
	case SH_ETH_REG_GIGABIT:

		reg_offset = sh_eth_offset_gigabit;

		break;

	case SH_ETH_REG_FAST_RZ:

		reg_offset = sh_eth_offset_fast_rz;

		break;

	case SH_ETH_REG_FAST_RCAR:

		reg_offset = sh_eth_offset_fast_rcar;

		break;

drivers/net/ethernet/renesas/sh_eth.h

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,6 @@ enum { 


enum {

	SH_ETH_REG_GIGABIT,

	SH_ETH_REG_FAST_RZ,

	SH_ETH_REG_FAST_RCAR,

	SH_ETH_REG_FAST_SH4,

	SH_ETH_REG_FAST_SH3_SH2
@@ -490,6 +489,7 @@ struct sh_eth_cpu_data { 
	unsigned apr:1;		/* EtherC has APR */

	unsigned mpr:1;		/* EtherC has MPR */

	unsigned tpauser:1;	/* EtherC has TPAUSER */

	unsigned gecmr:1;	/* EtherC has GECMR */

	unsigned bculr:1;	/* EtherC has BCULR */

	unsigned tsu:1;		/* EtherC has TSU */

	unsigned hw_swap:1;	/* E-DMAC has DE bit in EDMR */

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