Commit 8fb54284 authored by Santosh Shilimkar's avatar Santosh Shilimkar
Browse files

ARM: mm: Add strongly ordered descriptor support. 



On certain architectures, there might be a need to mark certain
addresses with strongly ordered memory attributes to avoid ordering
issues at the interconnect level.

On OMAP4, the asynchronous bridge buffers can only be drained
with strongly ordered accesses and hence the need to mark the
memory strongly ordered.

Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: default avatarWoodruff Richard <r-woodruff2@ti.com>
Tested-by: default avatarVishwanath BS <vishwanath.bs@ti.com>
parent 48af9fea

arch/arm/include/asm/mach/map.h

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ struct map_desc { 
#define MT_MEMORY_NONCACHED	11

#define MT_MEMORY_DTCM		12

#define MT_MEMORY_ITCM		13

#define MT_MEMORY_SO		14



#ifdef CONFIG_MMU

extern void iotable_init(struct map_desc *, int);

arch/arm/include/asm/pgtable.h

+3 −0
Original line number Diff line number Diff line
@@ -232,6 +232,9 @@ extern pgprot_t pgprot_kernel; 
#define pgprot_writecombine(prot) \

	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)



#define pgprot_stronglyordered(prot) \

	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)



#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE

#define pgprot_dmacoherent(prot) \

	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)

arch/arm/mm/mmu.c

+8 −0
Original line number Diff line number Diff line
@@ -273,6 +273,14 @@ static struct mem_type mem_types[] = { 
		.prot_l1   = PMD_TYPE_TABLE,

		.domain    = DOMAIN_KERNEL,

	},

	[MT_MEMORY_SO] = {

		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |

				L_PTE_MT_UNCACHED,

		.prot_l1   = PMD_TYPE_TABLE,

		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |

				PMD_SECT_UNCACHED | PMD_SECT_XN,

		.domain    = DOMAIN_KERNEL,

	},

};



const struct mem_type *get_mem_type(unsigned int type)

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