drm/i915: Replace intel_ddi_pll_init() (8f91cfd2) · Commits · 戴 / test

drivers/gpu/drm/i915/intel_dpll_mgr.c

+0 −25

Original line number	Diff line number	Diff line
		@@ -1881,27 +1881,6 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
		.get_hw_state = bxt_ddi_pll_get_hw_state,
		};

		static void intel_ddi_pll_init(struct drm_device *dev)
		{
		struct drm_i915_private *dev_priv = to_i915(dev);

		if (INTEL_GEN(dev_priv) < 9) {
		u32 val = I915_READ(LCPLL_CTL);

		/*
		* The LCPLL register should be turned on by the BIOS. For now
		* let's just check its state and print errors in case
		* something is wrong. Don't even try to turn it on.
		*/

		if (val & LCPLL_CD_SOURCE_FCLK)
		DRM_ERROR("CDCLK source is not LCPLL\n");

		if (val & LCPLL_PLL_DISABLE)
		DRM_ERROR("LCPLL is disabled\n");
		}
		}

		struct intel_dpll_mgr {
		const struct dpll_info *dpll_info;

		@@ -3305,10 +3284,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
		mutex_init(&dev_priv->dpll_lock);

		BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);

		/* FIXME: Move this to a more suitable place */
		if (HAS_DDI(dev_priv))
		intel_ddi_pll_init(dev);
		}

		/**

+21 −1

Original line number	Diff line number	Diff line
		@@ -3625,6 +3625,23 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
		I915_WRITE(MBUS_ABOX_CTL, val);
		}

		static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
		{
		u32 val = I915_READ(LCPLL_CTL);

		/*
		* The LCPLL register should be turned on by the BIOS. For now
		* let's just check its state and print errors in case
		* something is wrong. Don't even try to turn it on.
		*/

		if (val & LCPLL_CD_SOURCE_FCLK)
		DRM_ERROR("CDCLK source is not LCPLL\n");

		if (val & LCPLL_PLL_DISABLE)
		DRM_ERROR("LCPLL is disabled\n");
		}

		static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
		bool enable)
		{
		@@ -4085,7 +4102,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
		mutex_unlock(&power_domains->lock);
		assert_ved_power_gated(i915);
		assert_isp_power_gated(i915);
		} else if (IS_IVYBRIDGE(i915) \|\| INTEL_GEN(i915) >= 7) {
		} else if (IS_BROADWELL(i915) \|\| IS_HASWELL(i915)) {
		hsw_assert_cdclk(i915);
		intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
		} else if (IS_IVYBRIDGE(i915)) {
		intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915));
		}