Commit 8f74e861 authored by Suman Tripathi's avatar Suman Tripathi Committed by Duc Dang
Browse files

arm64: dts: Add the arasan mmc DTS entries for APM X-Gene v1 SoC 



This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene v1 SoC platforms.

[dhdang: changelog]
Signed-off-by: default avatarSuman Tripathi <stripathi@apm.com>
Signed-off-by: default avatarDuc Dang <dhdang@apm.com>
parent 8005c49d

arch/arm64/boot/dts/apm/apm-mustang.dts

+4 −0
Original line number Diff line number Diff line
@@ -74,3 +74,7 @@ 
&xgenet {

	status = "ok";

};



&mmc0 {

	status = "ok";

};

arch/arm64/boot/dts/apm/apm-storm.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -150,6 +150,40 @@ 
				clock-output-names = "socplldiv2";

			};



			ahbclk: ahbclk@1f2ac000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2ac000 0x0 0x1000

					0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg", "div-reg";

				csr-offset = <0x0>;

				csr-mask = <0x1>;

				enable-offset = <0x8>;

				enable-mask = <0x1>;

				divider-offset = <0x164>;

				divider-width = <0x5>;

				divider-shift = <0x0>;

				clock-output-names = "ahbclk";

			};



			sdioclk: sdioclk@1f2ac000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2ac000 0x0 0x1000

					0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg", "div-reg";

				csr-offset = <0x0>;

				csr-mask = <0x2>;

				enable-offset = <0x8>;

				enable-mask = <0x2>;

				divider-offset = <0x178>;

				divider-width = <0x8>;

				divider-shift = <0x0>;

				clock-output-names = "sdioclk";

			};



			qmlclk: qmlclk {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;
@@ -686,6 +720,16 @@ 
			interrupts = <0x0 0x4f 0x4>;

		};



		mmc0: mmc@1c000000 {

			compatible = "arasan,sdhci-4.9a";

			reg = <0x0 0x1c000000 0x0 0x100>;

			interrupts = <0x0 0x49 0x4>;

			dma-coherent;

			no-1-8-v;

			clock-names = "clk_xin", "clk_ahb";

			clocks = <&sdioclk 0>, <&ahbclk 0>;

		};



		phy1: phy@1f21a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f21a000 0x0 0x100>;

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